Patents by Inventor I-Chang Wang
I-Chang Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240086590Abstract: An adaptive grid generating method includes obtaining a first three-dimensional grid of a target structure; importing the first three-dimensional grid into a computer-aided engineering software to obtain a first two-dimensional planar grid; importing the first two-dimensional planar grid into a grid cleaning software to obtain a second two-dimensional planar grid; and importing the second two-dimensional planar grid into the computer-aided engineering software to obtain a second three-dimensional grid.Type: ApplicationFiled: June 12, 2023Publication date: March 14, 2024Applicants: Inventec (Pudong) Technology Corp., Inventec CorporationInventors: Hsueh-Liang Chen, Chen-Chou Huang, I-Chang Wang, Tzung-Shian Hung
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Publication number: 20240071818Abstract: A semiconductor device and method of fabricating the same include a substrate, a first epitaxial layer, a first protection layer, and a contact etching stop layer. The substrate includes a PMOS transistor region, and the first epitaxial layer is disposed on the substrate, within the PMOS transistor region. The first protection layer is disposed on the first epitaxial layer, covering surfaces of the first epitaxial layer. The contact etching stop layer is disposed on the first protection layer and the substrate, wherein a portion of the first protection layer is exposed from the contact etching stop layer.Type: ApplicationFiled: September 22, 2022Publication date: February 29, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: I-Wei Chi, Te-Chang Hsu, Yao-Jhan Wang, Meng-Yun Wu, Chun-Jen Huang
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Patent number: 10068979Abstract: A fin-shaped field effect transistor includes a substrate and a gate. The substrate includes an active area, where the active area includes a fin structure having at least an extension part protruding from the fin structure. The gate is disposed over the fin structure and directly on the extension part. The present invention also provides a planar field effect transistor including a substrate and a gate. The substrate includes an active area, where the active area includes a frame area and a penetrating area penetrating through the frame area. The gate is disposed over the active area, where the gate is directly disposed on the penetrating area, and the frame area at least at a side of the gate constitutes a source/drain surrounding an isolation island.Type: GrantFiled: August 15, 2017Date of Patent: September 4, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yi Chuen Eng, Teng-Chuan Hu, I-Chang Wang, Wei-Chih Chen, Hsiu-Kuan Hsu
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Patent number: 9923071Abstract: A fin-shaped field effect transistor includes a substrate and a gate. The substrate includes an active area, where the active area includes a fin structure having at least an extension part protruding from the fin structure. The gate is disposed over the fin structure and directly on the extension part. The present invention also provides a planar field effect transistor including a substrate and a gate. The substrate includes an active area, where the active area includes a frame area and a penetrating area penetrating through the frame area. The gate is disposed over the active area, where the gate is directly disposed on the penetrating area, and the frame area at least at a side of the gate constitutes a source/drain surrounding an isolation island.Type: GrantFiled: August 21, 2017Date of Patent: March 20, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yi Chuen Eng, Teng-Chuan Hu, I-Chang Wang, Wei-Chih Chen, Hsiu-Kuan Hsu
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Publication number: 20180012971Abstract: A fin-shaped field effect transistor includes a substrate and a gate. The substrate includes an active area, where the active area includes a fin structure having at least an extension part protruding from the fin structure. The gate is disposed over the fin structure and directly on the extension part. The present invention also provides a planar field effect transistor including a substrate and a gate. The substrate includes an active area, where the active area includes a frame area and a penetrating area penetrating through the frame area. The gate is disposed over the active area, where the gate is directly disposed on the penetrating area, and the frame area at least at a side of the gate constitutes a source/drain surrounding an isolation island.Type: ApplicationFiled: August 15, 2017Publication date: January 11, 2018Inventors: YI CHUEN ENG, Teng-Chuan Hu, I-Chang Wang, Wei-Chih Chen, Hsiu-Kuan Hsu
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Publication number: 20170352736Abstract: A fin-shaped field effect transistor includes a substrate and a gate. The substrate includes an active area, where the active area includes a fin structure having at least an extension part protruding from the fin structure. The gate is disposed over the fin structure and directly on the extension part. The present invention also provides a planar field effect transistor including a substrate and a gate. The substrate includes an active area, where the active area includes a frame area and a penetrating area penetrating through the frame area. The gate is disposed over the active area, where the gate is directly disposed on the penetrating area, and the frame area at least at a side of the gate constitutes a source/drain surrounding an isolation island.Type: ApplicationFiled: August 21, 2017Publication date: December 7, 2017Inventors: YI CHUEN ENG, Teng-Chuan Hu, I-Chang Wang, Wei-Chih Chen, Hsiu-Kuan Hsu
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Publication number: 20170309708Abstract: A field effect transistor is provided in the present invention with an active area including a source region, a drain region, and a channel region. The width of the channel region is larger than the width of the source/drain regions, and at least one of the source region and the drain region is comb-shaped.Type: ApplicationFiled: June 1, 2016Publication date: October 26, 2017Inventors: YI CHUEN ENG, Teng-Chuan Hu, I-Chang Wang, Wei-Chih Chen, Ming-Chih Chen
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Patent number: 9773880Abstract: A fin-shaped field effect transistor includes a substrate and a gate. The substrate includes an active area, where the active area includes a fin structure having at least an extension part protruding from the fin structure. The gate is disposed over the fin structure and directly on the extension part. The present invention also provides a planar field effect transistor including a substrate and a gate. The substrate includes an active area, where the active area includes a frame area and a penetrating area penetrating through the frame area. The gate is disposed over the active area, where the gate is directly disposed on the penetrating area, and the frame area at least at a side of the gate constitutes a source/drain surrounding an isolation island.Type: GrantFiled: October 7, 2015Date of Patent: September 26, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yi Chuen Eng, Teng-Chuan Hu, I-Chang Wang, Wei-Chih Chen, Hsiu-Kuan Hsu
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Publication number: 20170069730Abstract: A fin-shaped field effect transistor includes a substrate and a gate. The substrate includes an active area, where the active area includes a fin structure having at least an extension part protruding from the fin structure. The gate is disposed over the fin structure and directly on the extension part. The present invention also provides a planar field effect transistor including a substrate and a gate. The substrate includes an active area, where the active area includes a frame area and a penetrating area penetrating through the frame area. The gate is disposed over the active area, where the gate is directly disposed on the penetrating area, and the frame area at least at a side of the gate constitutes a source/drain surrounding an isolation island.Type: ApplicationFiled: October 7, 2015Publication date: March 9, 2017Inventors: YI CHUEN ENG, Teng-Chuan Hu, I-Chang Wang, Wei-Chih Chen, Hsiu-Kuan Hsu
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Patent number: 9318571Abstract: A gate structure includes a gate disposed on a substrate, a first spacer disposed on the substrate and surrounding the gate and a second spacer disposed on the first spacer and surrounding the gate, the second spacer is lower than the first spacer.Type: GrantFiled: February 23, 2009Date of Patent: April 19, 2016Assignee: UNITED MICROELECTRONICS CORP.Inventors: I-Chang Wang, Ming-Tsung Chen, Ling-Chun Chou, Po-Chao Tsao, Tsung-Hung Chang, Hui-Ling Chen, Cheng-Yen Wu, Chieh-Te Chen, Shin-Chi Chen
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Patent number: 9312258Abstract: A strained silicon substrate structure includes a first transistor and a second transistor disposed on a substrate. The first transistor includes a first gate structure and two first source/drain regions disposed at two sides of the first gate structure. A first source/drain to gate distance is between each first source/drain region and the first gate structure. The second transistor includes a second gate structure and two source/drain doped regions disposed at two side of the second gate structure. A second source/drain to gate distance is between each second source/drain region and the second gate structure. The first source/drain to gate distance is smaller than the second source/drain to gate distance.Type: GrantFiled: July 8, 2013Date of Patent: April 12, 2016Assignee: UNITED MICROELECTRONICS CORP.Inventors: Guang-Yaw Hwang, Ling-Chun Chou, I-Chang Wang, Shin-Chuan Huang, Jiunn-Hsiung Liao, Shin-Chi Chen, Pau-Chung Lin, Chiu-Hsien Yeh, Chin-Cheng Chien, Chieh-Te Chen
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Patent number: 9269811Abstract: A manufacturing method for a semiconductor device includes providing a substrate having at least agate structure formed thereon and a first spacer formed on sidewalls of the gate structure, performing an ion implantation to implant dopants into the substrate, forming a disposal spacer having at least a carbon-containing layer on the sidewalls of the gate structure, the carbon-containing layer contacting the first spacer, and performing a thermal treatment to form a protecting layer between the carbon-containing layer and the first spacer.Type: GrantFiled: December 26, 2014Date of Patent: February 23, 2016Assignee: UNITED MICROELECTRONICS CORP.Inventors: Ling-Chun Chou, I-Chang Wang, Ching-Wen Hung
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Publication number: 20150108553Abstract: A manufacturing method for a semiconductor device includes providing a substrate having at least agate structure formed thereon and a first spacer formed on sidewalls of the gate structure, performing an ion implantation to implant dopants into the substrate, forming a disposal spacer having at least a carbon-containing layer on the sidewalls of the gate structure, the carbon-containing layer contacting the first spacer, and performing a thermal treatment to form a protecting layer between the carbon-containing layer and the first spacer.Type: ApplicationFiled: December 26, 2014Publication date: April 23, 2015Inventors: Ling-Chun Chou, I-Chang Wang, Ching-Wen Hung
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Patent number: 8951876Abstract: A manufacturing method for a semiconductor device includes providing a substrate having at least a gate structure formed thereon and a first spacer formed on sidewalls of the gate structure, performing an ion implantation to implant dopants into the substrate, forming a disposal spacer having at least a carbon-containing layer on the sidewalls of the gate structure, the carbon-containing layer contacting the first spacer, and performing a thermal treatment to form a protecting layer between the carbon-containing layer and the first spacer.Type: GrantFiled: June 20, 2012Date of Patent: February 10, 2015Assignee: United Microelectronics Corp.Inventors: Ling-Chun Chou, I-Chang Wang, Ching-Wen Hung
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Publication number: 20130341685Abstract: A manufacturing method for a semiconductor device includes providing a substrate having at least a gate structure formed thereon and a first spacer formed on sidewalls of the gate structure, performing an ion implantation to implant dopants into the substrate, forming a disposal spacer having at least a carbon-containing layer on the sidewalls of the gate structure, the carbon-containing layer contacting the first spacer, and performing a thermal treatment to form a protecting layer between the carbon-containing layer and the first spacer.Type: ApplicationFiled: June 20, 2012Publication date: December 26, 2013Inventors: Ling-Chun Chou, I-Chang Wang, Ching-Wen Hung
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Publication number: 20130292775Abstract: A strained silicon substrate structure includes a first transistor and a second transistor disposed on a substrate. The first transistor includes a first gate structure and two first source/drain regions disposed at two sides of the first gate structure. A first source/drain to gate distance is between each first source/drain region and the first gate structure. The second transistor includes a second gate structure and two source/drain doped regions disposed at two side of the second gate structure. A second source/drain to gate distance is between each second source/drain region and the second gate structure. The first source/drain to gate distance is smaller than the second source/drain to gate distance.Type: ApplicationFiled: July 8, 2013Publication date: November 7, 2013Inventors: Guang-Yaw Hwang, Ling-Chun Chou, I-Chang Wang, Shin-Chuan Huang, Jiunn-Hsiung Liao, Shin-Chi Chen, Pau-Chung Lin, Chiu-Hsien Yeh, Chin-Cheng Chien, Chieh-Te Chen
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Patent number: 8574978Abstract: A method for forming a semiconductor device includes firstly providing a gate structure disposed on a substrate and a first nitride material layer disposed on the gate structure, secondly performing a protective step to modify the first nitride material layer in the presence of oxygen, then forming a second nitride material layer on the substrate, and later performing a removal step to remove the second nitride material layer without substantially slashing the modified first nitride material layer.Type: GrantFiled: April 11, 2012Date of Patent: November 5, 2013Assignee: United Microelectronics Corp.Inventors: Ching-Wen Hung, Chih-Sen Huang, Ling-Chun Chou, I-Chang Wang
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Publication number: 20130273706Abstract: A method for forming a semiconductor device includes firstly providing a gate structure disposed on a substrate and a first nitride material layer disposed on the gate structure, secondly performing a protective step to modify the first nitride material layer in the presence of oxygen, then forming a second nitride material layer on the substrate, and later performing a removal step to remove the second nitride material layer without substantially slashing the modified first nitride material layer.Type: ApplicationFiled: April 11, 2012Publication date: October 17, 2013Inventors: Ching-Wen Hung, Chih-Sen Huang, Ling-Chun Chou, I-Chang Wang
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Patent number: 8552503Abstract: A strained silicon substrate structure includes a first transistor and a second transistor disposed on a substrate. The first transistor includes a first gate structure and two first source/drain regions disposed at two sides of the first gate structure. A first source/drain to gate distance is between each first source/drain region and the first gate structure. The second transistor includes a second gate structure and two source/drain doped regions disposed at two side of the second gate structure. A second source/drain to gate distance is between each second source/drain region and the second gate structure. The first source/drain to gate distance is smaller than the second source/drain to gate distance.Type: GrantFiled: November 30, 2010Date of Patent: October 8, 2013Assignee: United Microelectronics Corp.Inventors: Guang-Yaw Hwang, Ling-Chun Chou, I-Chang Wang, Shin-Chuan Huang, Jiunn-Hsiung Liao, Shin-Chi Chen, Pau-Chung Lin, Chiu-Hsien Yeh, Chin-Cheng Chien, Chieh-Te Chen
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Publication number: 20130171789Abstract: A method for manufacturing a semiconductor device includes providing a substrate having a first gate structure and a second gate structure formed thereon; blanketly forming a seal layer covering the first gate structure and the second gate structure on the substrate; performing a first ion implantation to form first light-doped drains (LDDs) in the substrate respectively at two sides of the first gate structure; and performing a second ion implantation to form second LDDs in the substrate respectively at two sides of the second gate structure; wherein at least one of the first ion implantation and the second ion implantation is performed to penetrate through the seal layer.Type: ApplicationFiled: January 4, 2012Publication date: July 4, 2013Inventors: Ling-Chun Chou, Shin-Chuan Huang, I-Chang Wang, Ching-Wen Hung, Buo-Chin Hsu, Yi-Han Ye