Patents by Inventor I-Che Lee
I-Che Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11894297Abstract: Disclosed are metal-insulator-metal capacitors and integrated chips. In one embodiment, a metal-insulator-metal capacitor includes N electrodes and (N?1) passivation layers, wherein the N electrodes and the (N?1) passivation layers are alternately stacked on a substrate. N is an integer larger than 1. Thicknesses of the N electrodes gradually increase in a direction parallel to a normal direction of the substrate.Type: GrantFiled: July 29, 2021Date of Patent: February 6, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: I-Che Lee
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Patent number: 11862665Abstract: A method of forming a semiconductor structure including a metal-insulator-metal (MIM) capacitor includes: forming a stack structure over a substrate, wherein the stack structure includes a plurality of electrode material layers and a plurality of insulating material layers alternately stacked over the substrate; forming a mask layer on the stack structure; and performing a patterning process on the stack structure, so as to form the MIM capacitor comprising alternately stacked electrodes and insulating layers. Performing the patterning process includes: performing a first etching process to remove a first portion of the stack structure exposed by the mask layer; performing a first trimming process on the mask layer to remove a portion of the mask layer, and a first trimmed mask layer is formed; and performing a second etching process to remove a second portion of the stack structure exposed by the first trimmed mask layer.Type: GrantFiled: July 16, 2021Date of Patent: January 2, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: I-Che Lee
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Patent number: 11856793Abstract: A memory array and a method for forming the memory array are disclosed. The memory array includes memory elements, selectors and conductive vias. Each selector includes two pairs of fin structures. The conductive vias are electrically coupled to the two pairs of fin structures of the selectors.Type: GrantFiled: July 25, 2022Date of Patent: December 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: I-Che Lee, Huai-Ying Huang
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Publication number: 20230386941Abstract: Costs may be avoided and yields improved by applying scanning probe microscopy to substrates in the midst of an integrated circuit fabrication process sequence. Scanning probe microscopy may be used to provide conductance data. Conductance data may relate to device characteristics that are normally not available until the conclusion of device manufacturing. The substrates may be selectively treated to ameliorate a condition revealed by the data. Some substrates may be selectively discarded based on the data to avoid the expense of further processing. A process maintenance operation may be selectively carried out based on the data.Type: ApplicationFiled: July 26, 2023Publication date: November 30, 2023Inventors: I-Che Lee, Huai-Ying Huang
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Publication number: 20230366833Abstract: A semiconductor device inspection method including: depositing a dielectric material over a substrate to form an interconnect-level dielectric (ILD) layer; patterning the ILD layer to form via structures in the ILD layer; depositing an electrically conductive material to form an inspection layer on the ILD layer and in the via structures; imaging the inspection layer to generate image data; and detecting any defects in the via structures by analyzing the image data.Type: ApplicationFiled: July 26, 2023Publication date: November 16, 2023Inventors: I-Che Lee, Huai-Ying Huang
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Publication number: 20230360976Abstract: Various embodiments of the present disclosure are directed towards a method for nondestructive inspection of cell etch redeposition. In some embodiments of the method, a grayscale image of a plurality of cells on a wafer is captured. The grayscale image provides a top down view of the cells and, in some embodiments, is captured in situ after etching to form the cells. The cells are identified in the grayscale image to determine non-region of interest (non-ROI) pixels corresponding to the cells. The non-ROI pixels are subtracted from the grayscale image to determine ROI pixels. The ROI pixels are remaining pixels after the subtracting and correspond to material on sidewalls of, and in recesses between, the cells. An amount of etch redeposition on the sidewalls and in the recesses is then scored based on gray levels of the ROI pixels. Further, the wafer is processed based on the score.Type: ApplicationFiled: July 14, 2023Publication date: November 9, 2023Inventors: I-Che Lee, Huai-Ying Huang, Yi Chien Lee
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Patent number: 11761905Abstract: A semiconductor device inspection method including: depositing a dielectric material over a substrate to form an interconnect-level dielectric (ILD) layer; patterning the ILD layer to form via structures in the ILD layer; depositing an electrically conductive material to form an inspection layer on the ILD layer and in the via structures; imaging the inspection layer to generate image data; and detecting any defects in the via structures by analyzing the image data.Type: GrantFiled: August 26, 2021Date of Patent: September 19, 2023Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: I-Che Lee, Huai-Ying Huang
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Patent number: 11749569Abstract: Various embodiments of the present disclosure are directed towards a method for non-destructive inspection of cell etch redeposition. In some embodiments of the method, a grayscale image of a plurality of cells on a wafer is captured. The grayscale image provides a top down view of the cells and, in some embodiments, is captured in situ after etching to form the cells. The cells are identified in the grayscale image to determine non-region of interest (non-ROI) pixels corresponding to the cells. The non-ROI pixels are subtracted from the grayscale image to determine ROI pixels. The ROI pixels are remaining pixels after the subtracting and correspond to material on sidewalls of, and in recesses between, the cells. An amount of etch redeposition on the sidewalls and in the recesses is then scored based on gray levels of the ROI pixels. Further, the wafer is processed based on the score.Type: GrantFiled: September 30, 2020Date of Patent: September 5, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: I-Che Lee, Huai-Ying Huang, Yi Chien Lee
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Publication number: 20230097518Abstract: A method includes setting a current level of a write signal to a first non-zero value for a first period of time. The write signal is provided to a memory element during the first period of time. The current level of the write signal is adjusted from the first non-zero value to a second non-zero value, different from the first non-zero value, for a second period of time. The write signal is provided to the memory element during the second period of time. The current level of the write signal is adjusted from the second non-zero value to a third value, different from the first non-zero value and different from the second non-zero value, for a third period of time. The write signal is provided to the memory element during the third period of time.Type: ApplicationFiled: December 8, 2022Publication date: March 30, 2023Inventors: I-Che Lee, Huai-Ying Huang
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Publication number: 20230060557Abstract: A semiconductor device inspection method including: depositing a dielectric material over a substrate to form an interconnect-level dielectric (ILD) layer; patterning the ILD layer to form via structures in the ILD layer; depositing an electrically conductive material to form an inspection layer on the ILD layer and in the via structures; imaging the inspection layer to generate image data; and detecting any defects in the via structures by analyzing the image data.Type: ApplicationFiled: August 26, 2021Publication date: March 2, 2023Inventors: I-Che LEE, Huai-Ying Huang
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Publication number: 20230030826Abstract: Disclosed are metal-insulator-metal capacitors and integrated chips. In one embodiment, a metal-insulator-metal capacitor includes N electrodes and (N?1) passivation layers, wherein the N electrodes and the (N?1) passivation layers are alternately stacked on a substrate. N is an integer larger than 1. Thicknesses of the N electrodes gradually increase in a direction parallel to a normal direction of the substrate.Type: ApplicationFiled: July 29, 2021Publication date: February 2, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: I-Che Lee
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Publication number: 20230017938Abstract: A method of forming a semiconductor structure including a metal-insulator-metal (MIM) capacitor includes: forming a stack structure over a substrate, wherein the stack structure includes a plurality of electrode material layers and a plurality of insulating material layers alternately stacked over the substrate; forming a mask layer on the stack structure; and performing a patterning process on the stack structure, so as to form the MIM capacitor comprising alternately stacked electrodes and insulating layers. Performing the patterning process includes: performing a first etching process to remove a first portion of the stack structure exposed by the mask layer; performing a first trimming process on the mask layer to remove a portion of the mask layer, and a first trimmed mask layer is formed; and performing a second etching process to remove a second portion of the stack structure exposed by the first trimmed mask layer.Type: ApplicationFiled: July 16, 2021Publication date: January 19, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: I-Che Lee
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Patent number: 11527289Abstract: A method includes setting a current level of a write signal to a first non-zero value for a first period of time. The write signal is provided to a memory element during the first period of time. The current level of the write signal is adjusted from the first non-zero value to a second non-zero value, different from the first non-zero value, for a second period of time. The write signal is provided to the memory element during the second period of time. The current level of the write signal is adjusted from the second non-zero value to a third value, different from the first non-zero value and different from the second non-zero value, for a third period of time. The write signal is provided to the memory element during the third period of time.Type: GrantFiled: March 12, 2021Date of Patent: December 13, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: I-Che Lee, Huai-Ying Huang
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Publication number: 20220359612Abstract: A memory array and a method for forming the memory array are disclosed. The memory array includes memory elements, selectors and conductive vias. Each selector includes two pairs of fin structures. The conductive vias are electrically coupled to the two pairs of fin structures of the selectors.Type: ApplicationFiled: July 25, 2022Publication date: November 10, 2022Inventors: I-CHE LEE, HUAI-YING HUANG
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Publication number: 20220293175Abstract: A method includes setting a current level of a write signal to a first non-zero value for a first period of time. The write signal is provided to a memory element during the first period of time. The current level of the write signal is adjusted from the first non-zero value to a second non-zero value, different from the first non-zero value, for a second period of time. The write signal is provided to the memory element during the second period of time. The current level of the write signal is adjusted from the second non-zero value to a third value, different from the first non-zero value and different from the second non-zero value, for a third period of time. The write signal is provided to the memory element during the third period of time.Type: ApplicationFiled: March 12, 2021Publication date: September 15, 2022Inventors: I-Che Lee, Huai-Ying Huang
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Patent number: 11404477Abstract: A memory array and a method for forming the memory array are disclosed. The memory array includes memory elements, selectors and conductive vias. Each selector includes two pairs of fin structures and a gate structure. The gate structure crosses the two pairs of fin structures. The conductive vias are electrically coupled to the two pairs of fin structures of the selectors.Type: GrantFiled: August 31, 2020Date of Patent: August 2, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: I-Che Lee, Huai-Ying Huang
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Publication number: 20220238390Abstract: Costs may be avoided and yields improved by applying scanning probe microscopy to substrates in the midst of an integrated circuit fabrication process sequence. Scanning probe microscopy may be used to provide conductance data. Conductance data may relate to device characteristics that are normally not available until the conclusion of device manufacturing. The substrates may be selectively treated to ameliorate a condition revealed by the data. Some substrates may be selectively discarded based on the data to avoid the expense of further processing. A process maintenance operation may be selectively carried out based on the data.Type: ApplicationFiled: March 12, 2021Publication date: July 28, 2022Inventors: I-Che Lee, Huai-Ying Huang
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Publication number: 20220238438Abstract: A second metal structure such as a metal plug is formed over a first metal structure, such as a metal line, by causing metal material from the first metal structure to migrate into an opening in a dielectric layer over the first metal structure. The metal material, which may be copper, is of a type that undergoes a reduction in density as it oxidizes. Migration is induced using gases that alternately oxidize and reduce the metal material. Over many cycles, the metal material migrates into the opening. In some embodiments, the migrated metal material partially fills the opening. In some embodiments, the migrated metal material completely fills the opening.Type: ApplicationFiled: May 5, 2021Publication date: July 28, 2022Inventors: I-Che Lee, Huai-Ying Huang, Ruei-Cheng Shiu
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Patent number: 11389605Abstract: A valve assembly attached to a capacitor such that pressurizing the capacitor to a first positive pressure threshold induces the valve assembly to open, the pressurized air is released to the patient, and then as the pressure in the capacitor drops to a second pressure threshold the valve closes and the capacitor begins to build pressure until the first positive pressure threshold is achieved and the process repeats. Relative to the valve assembly and integrated therein, is an incrementally adjustable index knob to vary the rate of a biasing force performing work against the actionable valve face of the diaphragm functional surface to set the performance of the valve assembly, thereby increasing the potential for correct operation across a range of oscillating rates supporting a broad spectrum of patient therapies and types.Type: GrantFiled: February 12, 2019Date of Patent: July 19, 2022Assignee: Vortran Medical Technology I, Inc.Inventors: James I-Che Lee, Abdolreza Saied, Glen M. Thomson
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Publication number: 20220069010Abstract: A memory array and a method for forming the memory array are disclosed. The memory array includes memory elements, selectors and conductive vias. Each selector includes two pairs of fin structures and a gate structure. The gate structure crosses the two pairs of fin structures. The conductive vias are electrically coupled to the two pairs of fin structures of the selectors.Type: ApplicationFiled: August 31, 2020Publication date: March 3, 2022Inventors: I-CHE LEE, HUAI-YING HUANG