Patents by Inventor I-Hsien Chen
I-Hsien Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12002712Abstract: A method includes forming a first metallic feature, forming a dielectric layer over the first metallic feature, etching the dielectric layer to form an opening, with a top surface of the first metallic feature being exposed through the opening, and performing a first treatment on the top surface of the first metallic feature. The first treatment is performed through the opening, and the first treatment is performed using a first process gas. After the first treatment, a second treatment is performed through the opening, and the second treatment is performed using a second process gas different from the first process gas. A second metallic feature is deposited in the opening.Type: GrantFiled: June 30, 2022Date of Patent: June 4, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chun-Hsien Huang, I-Li Chen, Pin-Wen Chen, Yuan-Chen Hsu, Wei-Jung Lin, Chih-Wei Chang, Ming-Hsing Tsai
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Publication number: 20240170343Abstract: A semiconductor device includes a first set of nanostructures stacked over a substrate in a vertical direction, and each of the first set of nanostructures includes a first end portion and a second end portion, and a first middle portion laterally between the first end portion and the second end portion. The first end portion and the second end portion are thicker than the first middle portion. The semiconductor device also includes a first plurality of semiconductor capping layers around the first middle portions of the first set of nanostructures, and a gate structure around the first plurality of semiconductor capping layers.Type: ApplicationFiled: January 24, 2024Publication date: May 23, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Sai-Hooi YEONG, Bo-Feng YOUNG, Chi-On CHUI, Chih-Chieh YEH, Cheng-Hsien WU, Chih-Sheng CHANG, Tzu-Chiang CHEN, I-Sheng CHEN
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Publication number: 20240131010Abstract: In some embodiments of the present disclosure, a sustained release osmotic-controlled pharmaceutical composition is provided, including: a core and a semi-permeable membrane coated on the core. The core includes a drug compartment, in which the drug compartment includes a first active ingredient, a first polymer and a first osmogen, and the first active ingredient includes lurasidone, a pharmaceutical acceptable salt of the lurasidone or a combination thereof. The semi-permeable membrane includes a membrane body and at least one pore distributed in the membrane body.Type: ApplicationFiled: October 15, 2023Publication date: April 25, 2024Inventors: Chun-You LIOU, Tzu-Hsien CHAN, Hua-Jing JHAN, I-Hsiang LIU, Tse-Hsien CHEN, Chi-Heng JIAN
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Publication number: 20240126861Abstract: A device unlocking method and an electronic device are provided. The method includes: detecting fingerprint information of a user by a first sensor of the electronic device; authenticating the fingerprint information and temporarily storing an authentication result of the fingerprint information; after authenticating the fingerprint information, detecting operation environment information related to the electronic device by a second sensor of the electronic device; and in response to the operation environment information meeting a default condition, unlocking the electronic device according to the authentication result.Type: ApplicationFiled: May 9, 2023Publication date: April 18, 2024Applicant: ASUSTeK COMPUTER INC.Inventors: Chih-Hsien Yang, Hui-Fen Chen, I-Hsi Wu
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Publication number: 20240105778Abstract: A semiconductor device includes a fin extending from a substrate. The fin has a source/drain region and a channel region. The channel region includes a first semiconductor layer and a second semiconductor layer disposed over the first semiconductor layer and vertically separated from the first semiconductor layer by a spacing area. A high-k dielectric layer at least partially wraps around the first semiconductor layer and the second semiconductor layer. A metal layer is formed along opposing sidewalls of the high-k dielectric layer. The metal layer includes a first material. The spacing area is free of the first material.Type: ApplicationFiled: December 1, 2023Publication date: March 28, 2024Inventors: I-Sheng CHEN, Yee-Chia YEO, Chih Chieh YEH, Cheng-Hsien WU
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Patent number: 11923252Abstract: A semiconductor device includes a first set of nanostructures stacked over a substrate in a vertical direction, and each of the first set of nanostructures includes a first end portion and a second end portion, and a first middle portion laterally between the first end portion and the second end portion. The first end portion and the second end portion are thicker than the first middle portion. The semiconductor device also includes a first plurality of semiconductor capping layers around the first middle portions of the first set of nanostructures, and a gate structure around the first plurality of semiconductor capping layers.Type: GrantFiled: January 27, 2021Date of Patent: March 5, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Sai-Hooi Yeong, Bo-Feng Young, Chi-On Chui, Chih-Chieh Yeh, Cheng-Hsien Wu, Chih-Sheng Chang, Tzu-Chiang Chen, I-Sheng Chen
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Publication number: 20150261961Abstract: A scenario-based security method and system are provided. The scenario-based security method includes a) establishing a correspondence table, the correspondence table records an account related to a first feature code and a second feature code; b) programming a standard process and a scenario-based process, the first feature code is assigned to the standard process, and the second feature code is assigned to the scenario-based process; c) a security processing module connected to the correspondence table; and d) the standard process is performed after the security processing module receiving the first feature code, or the scenario-based process is performed after the security processing module receiving the second feature code. The present invention is to provide at least one of two scenario-based feature codes related with a single account to perform a part of normal process, thereby preventing a person held the account is maliciously attacked by a ruffian.Type: ApplicationFiled: March 17, 2014Publication date: September 17, 2015Inventors: I-Hsien CHEN, Siang-Ci LIU
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Patent number: 8270706Abstract: The present invention discloses a dynamic calibration method for a single and multiple video capture devices. The present invention can acquire the variations of the pan angle and tilt angle of a single video capture device according to the displacement of the feature points between successive images. For a plurality of video capture devices, the present invention includes the epipolar-plane constraint between a plurality of video capture devices to achieve the goal of dynamical calibration. The calibration method in the present invention does not require specific calibration patterns or complicated correspondence of feature points, and can be applied to surveillance systems with wide-range coverage.Type: GrantFiled: August 5, 2011Date of Patent: September 18, 2012Assignee: National Chiao Tung UniversityInventors: I-Hsien Chen, Sheng-Jyh Wang
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Patent number: 8150143Abstract: The present invention discloses a dynamic calibration method for a single and multiple video capture devices. The present invention can acquire the variations of the pan angle and tilt angle of a single video capture device according to the displacement of the feature points between successive images. For a plurality of video capture devices, the present invention includes the epipolar-plane constraint between a plurality of video capture devices to achieve the goal of dynamical calibration. The calibration method in the present invention does not require specific calibration patterns or complicated correspondence of feature points, and can be applied to surveillance systems with wide-range coverage.Type: GrantFiled: April 9, 2008Date of Patent: April 3, 2012Assignee: National Chiao Tung UniversityInventors: I-Hsien Chen, Sheng-Jyh Wang
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Publication number: 20110285858Abstract: The present invention discloses a dynamic calibration method for a single and multiple video capture devices. The present invention can acquire the variations of the pan angle and tilt angle of a single video capture device according to the displacement of the feature points between successive images. For a plurality of video capture devices, the present invention includes the epipolar-plane constraint between a plurality of video capture devices to achieve the goal of dynamical calibration. The calibration method in the present invention does not require specific calibration patterns or complicated correspondence of feature points, and can be applied to surveillance systems with wide-range coverage.Type: ApplicationFiled: August 5, 2011Publication date: November 24, 2011Applicant: NATIONAL CHIAO TUNG UNIVERSITYInventors: I-HSIEN CHEN, SHENG-JYH WANG
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Publication number: 20090208063Abstract: The present invention discloses a dynamic calibration method for a single and multiple video capture devices. The present invention can acquire the variations of the pan angle and tilt angle of a single video capture device according to the displacement of the feature points between successive images. For a plurality of video capture devices, the present invention includes the epipolar-plane constraint between a plurality of video capture devices to achieve the goal of dynamical calibration. The calibration method in the present invention does not require specific calibration patterns or complicated correspondence of feature points, and can be applied to surveillance systems with wide-range coverage.Type: ApplicationFiled: April 9, 2008Publication date: August 20, 2009Inventors: I-Hsien Chen, Sheng-Jyh Wang
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Publication number: 20070196016Abstract: A calibration system and a method to be used in an image capture apparatus are disclosed. The calibration system includes a calibration appliance, a feature extraction unit and a processor. The calibration appliance has a plurality of mark points. The plurality of mark points is on the same plane to form a line segment with a known length. The image capture apparatus captures an image. Then based on the captured image, the feature extraction unit extracts at least three image feature points corresponding to the mark points. The processor calculates the inclination angle of the image capture apparatus, and the height between the image capture apparatus and the plane. Besides a line segment with a known length, the mark points corresponding to the image feature points may form a corner with a known angle, two corners with unknown but equal angles, or two line segments with unknown but equal lengths. Convenience for the calibration system is therefore improved.Type: ApplicationFiled: July 11, 2006Publication date: August 23, 2007Inventors: I-Hsien Chen, Sheng-Jyh Wang
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Patent number: 7177783Abstract: The invention allows the inclusion of cross-talk coupling and other noise in circuit simulation by considering a resultant glitch in more detail than just its peak value. A set of parameters represents the noise, with an exemplary embodiment using a triangle approximation to a glitch based on a set of three parameters: the peak voltage value, the leading edge slope and the trailing edge slope. These values are then used as the input stimulus to a given cell instance in the network in which the resulting propagated noise values, also in a triangle approximation, are determined by a simulation. The results can be stored as a library so that, given the parameters of the input noise and the particular cell, a simulation can determine the propagated noise through a look-up process. To reduce the space requirements of the library, the dimensionality of the look-up tables can be reduced through the introduction of a set of auxiliary functions to offset error from this reduction.Type: GrantFiled: January 10, 2003Date of Patent: February 13, 2007Assignee: Cadence Design Systems, Inc.Inventors: Lifeng Wu, Jianlin Wei, I-Hsien Chen
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Patent number: 6826736Abstract: The present invention presents techniques for considering whether the effects of cross-talk coupling and other noise exceed the noise tolerance of a circuit. One aspect of the present invention uses a set of parameters to represent this noise. An exemplary embodiment uses a triangle or trapezoidal approximation to a glitch based on a set of parameters: the peak voltage value, the width, the leading edge slope and the trailing edge slope. These values are then used as the input of a library to look up the corresponding noise tolerance parameter set values. In a variation, a set of formulae can provide the noise tolerance parameter set values. In an exemplary embodiment, the noise tolerance parameter set is taken to include the minimum peak value for the noise to be possibly harmful and the minimum width value for the noise to be possibly harmful.Type: GrantFiled: January 10, 2003Date of Patent: November 30, 2004Assignee: Cadence Design Systems, Inc.Inventors: Lifeng Wu, Jianlin Wei, I-Hsien Chen
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Publication number: 20040216221Abstract: The present invention is to provide a dispensing device comprising a dispenser having an upper channel and a bottom opening for storing liquid cleaner; a connecting cup extended downward from the dispenser including at least one aperture on a bottom thereof; and a float in the connecting cup opposite the bottom opening. While the dispenser is mounted in a toilet tank, the float is adapted to either engage with or move away from the bottom opening as the water level in the toilet tank rises or falls. As such, the dispenser is adapted to automatically dispense liquid cleaner to the toilet tank or stop dispensing liquid cleaner to the toilet tank as the float falls or rises.Type: ApplicationFiled: December 2, 2003Publication date: November 4, 2004Applicant: CAPTAIN ASSET INVEST MANAGEMENT LIMITEDInventor: I-Hsien Chen
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Publication number: 20040015339Abstract: The present invention presents techniques for considering whether the effects of cross-talk coupling and other noise exceed the noise tolerance of a circuit. One aspect of the present invention uses a set of parameters to represent this noise. An exemplary embodiment uses a triangle or trapezoidal approximation to a glitch based on a set of parameters: the peak voltage value, the width, the leading edge slope and the trailing edge slope. These values are then used as the input of a library to look up the corresponding noise tolerance parameter set values. In a variation, a set of formulae can provide the noise tolerance parameter set values. In an exemplary embodiment, the noise tolerance parameter set is taken to include the minimum peak value for the noise to be possibly harmful and the minimum width value for the noise to be possibly harmful.Type: ApplicationFiled: January 10, 2003Publication date: January 22, 2004Applicant: Cadence Design Systems, Inc.Inventors: Lifeng Wu, Jianlin Wei, I-Hsien Chen
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Publication number: 20030229481Abstract: The invention allows the inclusion of cross-talk coupling and other noise in circuit simulation by considering the details a resultant glitch in more detail than just its peak value. A set of parameters represents the noise, with an exemplary embodiment using a triangle approximation to a glitch based on a set of three parameters: the peak voltage value, the leading edge slope and the trailing edge slope. These values are then used as the input stimulus to a given cell instance in the network in which the result propagated noise values, also in a triangle approximation, are determined by a simulation. The results can be stored as a library so that, given the parameters of the input noise and the particular cell, a simulation can determine the propagated noise through a look-up process. To reduce the space requirements of the library, the dimensionality of the look-up tables can be reduced through the introduction of a set of auxiliary functions to offset error from this reduction.Type: ApplicationFiled: January 10, 2003Publication date: December 11, 2003Inventors: Lifeng Wu, Jianlin Wei, I-Hsien Chen
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Patent number: 6278964Abstract: An approach for simulating hot carrier effects in an integrated circuit (IC) at the circuit level includes generating a hot carrier library of delay data for each cell in the IC, using the hot carrier library data to generate a set of scaled timing data for the IC and using the scaled timing data with a IC performance simulator to simulate the IC operation. The scaled timing data is based upon the cell delay data and time-based switching activity of each cell in the IC.Type: GrantFiled: May 29, 1998Date of Patent: August 21, 2001Assignees: Matsushita Electric Industrial Co., Ltd., BTA Technology Inc.Inventors: Jingkun Fang, Hirokazu Yonezawa, Lifeng Wu, Yoshiyuki Kawakami, Nobufusa Iwanishi, Alvin I-Hsien Chen, Norio Koike, Ping Chen, Chune-Sin Yeh, Zhihong Liu
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Patent number: D1018527Type: GrantFiled: May 12, 2020Date of Patent: March 19, 2024Assignee: COMPAL ELECTRONICS, INC.Inventors: Han-Tsai Liu, Jyh-Chyang Tzou, Cheng-Shiue Jan, Yao-Hsien Yang, Pai-Feng Chen, I-Hao Chen