Abstract: A method and an apparatus for self-calibration of a driving capability and a resistance of an on-die termination are provided. The apparatus includes an output interface physical layer (PHY) and a ring oscillator. The output interface PHY receives an operation voltage. The ring oscillator surrounds the output interface PHY to sense a work temperature or the operation voltage and accordingly outputs a sensing result. The driving capability or the resistance of the on-die termination of the output interface PHY is adjusted according to the sensing result.

Abstract: A memory control system includes a first queue unit, a second queue unit, a first transforming unit, a second transforming unit, an arbiter and a control unit. The first queue unit temporarily stores multiple first request instructions. The second queue unit temporarily stores multiple second request instructions. The first transforming unit selectively re-assigns memory addresses corresponding to these first request instructions. The second transforming unit selectively re-assigns memory addresses corresponding to these second request instructions. The arbiter performs immediate scheduling of the one or more first request instructions and the one or more second request instructions to the memory. The control unit compares bandwidths of the one or more first request instructions with bandwidths of the one or more second request instructions, and controls the first transforming unit and the second transforming unit to perform re-assigning operations or not according to compared results.

Abstract: A method and an apparatus for self-calibration of a driving capability and a resistance of an on-die termination are provided. The apparatus includes an output interface physical layer (PHY) and a ring oscillator. The output interface PHY receives an operation voltage. The ring oscillator surrounds the output interface PHY to sense a work temperature or the operation voltage and accordingly outputs a sensing result. The driving capability or the resistance of the on-die termination of the output interface PHY is adjusted according to the sensing result.

Abstract: A memory control system includes a first queue unit, a second queue unit, a first transforming unit, a second transforming unit, an arbiter and a control unit. The first queue unit temporarily stores multiple first request instructions. The second queue unit temporarily stores multiple second request instructions. The first transforming unit selectively re-assigns memory addresses corresponding to these first request instructions. The second transforming unit selectively re-assigns memory addresses corresponding to these second request instructions. The arbiter performs immediate scheduling of the one or more first request instructions and the one or more second request instructions to the memory. The control unit compares bandwidths of the one or more first request instructions with bandwidths of the one or more second request instructions, and controls the first transforming unit and the second transforming unit to perform re-assigning operations or not according to compared results.

Abstract: A memory control system includes a first queue unit, a second queue unit, a first transforming unit, a second transforming unit, an arbiter and a control unit. The first queue unit temporarily stores multiple first request instructions. The second queue unit temporarily stores multiple second request instructions. The first transforming unit selectively re-assigns memory addresses corresponding to these first request instructions. The second transforming unit selectively re-assigns memory addresses corresponding to these second request instructions. The arbiter performs immediate scheduling of the first request instructions and the second request instructions to the memory. The control unit compares bandwidths of the first request instructions with bandwidths of the second request instructions, and controls the first transforming unit and the second transforming unit to perform re-assigning operations or not according to compared results.

Abstract: A memory control system includes a first queue unit, a second queue unit, a first transforming unit, a second transforming unit, an arbiter and a control unit. The first queue unit temporarily stores multiple first request instructions. The second queue unit temporarily stores multiple second request instructions. The first transforming unit selectively re-assigns memory addresses corresponding to these first request instructions. The second transforming unit selectively re-assigns memory addresses corresponding to these second request instructions. The arbiter performs immediate scheduling of the first request instructions and the second request instructions to the memory. The control unit compares bandwidths of the first request instructions with bandwidths of the second request instructions, and controls the first transforming unit and the second transforming unit to perform re-assigning operations or not according to compared results.

Abstract: A dynamic memory access method includes following steps. First, many data access commands are received. Each of the data access commands accesses a dynamic memory according to a page address and a bank address. Next, whether an access data to be accessed by the corresponding data access command is an instantaneous data or a non-instantaneous data is determined. Then, the page and bank addresses of each of the data access commands are respectively compared with a previously page and bank addresses at a previous time used for accessing the dynamic memory, such that an address hit status is obtained. Next, a service sequence is generated according to whether each of the data access commands is an instantaneous or instantaneous data and the address hit status of the commands. Finally, each of the data access commands is executed to access the dynamic memory sequentially according to the service sequence.