Patents by Inventor Iain Craig Robertson
Iain Craig Robertson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11095474Abstract: A communication device configured to communicate according to a data protocol in which data is carried in packets over a serial data link and the communication device is arranged: to form packets for transmission over the link in such a way that every packet commences with a first bit value; and between transmitting successive packets to continuously transmit a second bit value opposite to the first bit value over the link.Type: GrantFiled: May 16, 2019Date of Patent: August 17, 2021Assignee: MENTOR GRAPHICS CORPORATIONInventors: Andrew Brian Thomas Hopkins, Iain Craig Robertson
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Patent number: 10437700Abstract: A method of tracing transactions on an integrated circuit chip. The method comprises, for each transaction: extracting the transaction from interconnect circuitry of the integrated circuit chip, the transaction comprising an address signal and a data signal; applying a filtering condition to the address signal; only if the address signal does not fail the filtering condition, storing the address signal in an address trace buffer; storing the data signal in a data trace buffer; applying a triggering condition to the stored transaction; and outputting the stored transaction if the stored transaction matches the triggering condition.Type: GrantFiled: August 19, 2016Date of Patent: October 8, 2019Assignee: UltraSoC Technologies LimitedInventors: Iain Craig Robertson, Andrew Brian Thomas Hopkins, Michael Jonathan Thyer
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Publication number: 20190273631Abstract: A communication device configured to communicate according to a data protocol in which data is carried in packets over a serial data link and the communication device is arranged: to form packets for transmission over the link in such a way that every packet commences with a first bit value; and between transmitting successive packets to continuously transmit a second bit value opposite to the first bit value over the link.Type: ApplicationFiled: May 16, 2019Publication date: September 5, 2019Inventors: Andrew Brian Thomas Hopkins, Iain Craig Robertson
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Patent number: 10326612Abstract: A communication device configured to communicate according to a data protocol in which data is carried in packets over a serial data link and the communication device is arranged: to form packets for transmission over the link in such a way that every packet commences with a first bit value; and between transmitting successive packets to continuously transmit a second bit value opposite to the first bit value over the link.Type: GrantFiled: August 24, 2016Date of Patent: June 18, 2019Assignee: UltraSoC Technologies LimitedInventors: Andrew Brian Thomas Hopkins, Iain Craig Robertson
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Patent number: 10296476Abstract: A method of profiling transactions on an integrated circuit chip. The method comprises, for each transaction: extracting the transaction from interconnect circuitry of the integrated circuit chip; and filtering the transaction at a filtering circuit to determine which passband a parameter of the transaction lies within; sending an increment signal to a counter of a bank of counters, the counter having a counter value indicative of a number of transactions having the parameter lying within the passband; and outputting the counter values of the bank of counters.Type: GrantFiled: August 12, 2016Date of Patent: May 21, 2019Assignee: UltraSoC Technologies LimitedInventors: Andrew Brian Thomas Hopkins, Michael Jonathan Thyer, Iain Craig Robertson
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Patent number: 9632138Abstract: A method of functionality testing system circuitry on an integrated circuit chip, the system circuitry comprising a plurality of sub-circuits and the integrated circuit chip further comprising debugging circuitry, the debugging circuitry comprising variability circuitry. The method comprises: at the system circuitry, performing a function by the sub-circuits performing concurrent actions; at the variability circuitry, altering relative timing of the concurrent actions so as to increase the likelihood of one or more errors in the system circuitry's performance of the function; and at the debugging circuitry, recording one or more errors in the system circuitry's performance of the function.Type: GrantFiled: October 9, 2015Date of Patent: April 25, 2017Assignee: ULTRASOC TECHNOLOGIES LIMITEDInventors: Andrew Brian Thomas Hopkins, Iain Craig Robertson, Michael Jonathan Thyer
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Publication number: 20170063570Abstract: A communication device configured to communicate according to a data protocol in which data is carried in packets over a serial data link and the communication device is arranged: to form packets for transmission over the link in such a way that every packet commences with a first bit value; and between transmitting successive packets to continuously transmit a second bit value opposite to the first bit value over the link.Type: ApplicationFiled: August 24, 2016Publication date: March 2, 2017Inventors: Andrew Brian Thomas Hopkins, Iain Craig Robertson
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Publication number: 20170052868Abstract: A method of tracing transactions on an integrated circuit chip. The method comprises, for each transaction: extracting the transaction from interconnect circuitry of the integrated circuit chip, the transaction comprising an address signal and a data signal; applying a filtering condition to the address signal; only if the address signal does not fail the filtering condition, storing the address signal in an address trace buffer; storing the data signal in a data trace buffer; applying a triggering condition to the stored transaction; and outputting the stored transaction if the stored transaction matches the triggering condition.Type: ApplicationFiled: August 19, 2016Publication date: February 23, 2017Inventors: Iain Craig Robertson, Andrew Brian Thomas Hopkins, Michael Jonathan Thyer
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Publication number: 20170046288Abstract: A method of profiling transactions on an integrated circuit chip. The method comprises, for each transaction: extracting the transaction from interconnect circuitry of the integrated circuit chip; and filtering the transaction at a filtering circuit to determine which passband a parameter of the transaction lies within; sending an increment signal to a counter of a bank of counters, the counter having a counter value indicative of a number of transactions having the parameter lying within the passband; and outputting the counter values of the bank of counters.Type: ApplicationFiled: August 12, 2016Publication date: February 16, 2017Inventors: Andrew Brian Thomas Hopkins, Michael Jonathan Thyer, Iain Craig Robertson
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Patent number: 9424166Abstract: An integrated circuit chip device comprising: system circuitry; debugging circuitry configured to debug the system circuitry, the debugging circuitry being segmented into zones; wherein the debugging circuitry comprises an interconnect fabric configured to route debug messages through a zone from a zone entry node of the interconnect fabric to a zone exit node of the interconnect fabric; and wherein the debugging circuitry is configured to, on receiving a debug message at a zone entry node that is shorter than a specified length, modify the debug message to form a modified debug message by increasing the length of the debug message to the specified length.Type: GrantFiled: April 11, 2014Date of Patent: August 23, 2016Assignee: ULTRASOC TECHNOLOGIES LIMITEDInventors: Andrew Brian Thomas Hopkins, Iain Craig Robertson
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Publication number: 20160033575Abstract: A method of functionality testing system circuitry on an integrated circuit chip, the system circuitry comprising a plurality of sub-circuits and the integrated circuit chip further comprising debugging circuitry, the debugging circuitry comprising variability circuitry. The method comprises: at the system circuitry, performing a function by the sub-circuits performing concurrent actions; at the variability circuitry, altering relative timing of the concurrent actions so as to increase the likelihood of one or more errors in the system circuitry's performance of the function; and at the debugging circuitry, recording one or more errors in the system circuitry's performance of the function.Type: ApplicationFiled: October 9, 2015Publication date: February 4, 2016Inventors: Andrew Brian Thomas Hopkins, Iain Craig Robertson, Michael Jonathan Thyer
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Patent number: 9188638Abstract: A method of functionality testing system circuitry on an integrated circuit chip, the system circuitry comprising a plurality of sub-circuits and the integrated circuit chip further comprising debugging circuitry, the debugging circuitry comprising variability circuitry. The method comprises: at the system circuitry, performing a function by the sub-circuits performing concurrent actions; at the variability circuitry, altering relative timing of the concurrent actions so as to increase the likelihood of one or more errors in the system circuitry's performance of the function; and at the debugging circuitry, recording one or more errors in the system circuitry's performance of the function.Type: GrantFiled: April 11, 2014Date of Patent: November 17, 2015Assignee: UltraSoC Technologies Ltd.Inventors: Andrew Brian Thomas Hopkins, Iain Craig Robertson, Michael Jonathan Thyer
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Publication number: 20150268302Abstract: An integrated circuit chip device comprising: system circuitry; debugging circuitry configured to debug the system circuitry, the debugging circuitry being segmented into zones; wherein the debugging circuitry comprises an interconnect fabric configured to route debug messages through a zone from a zone entry node of the interconnect fabric to a zone exit node of the interconnect fabric; and wherein the debugging circuitry is configured to, on receiving a debug message at a zone entry node that is shorter than a specified length, modify the debug message to form a modified debug message by increasing the length of the debug message to the specified length.Type: ApplicationFiled: April 11, 2014Publication date: September 24, 2015Inventors: Andrew Brian Thomas Hopkins, Iain Craig Robertson
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Patent number: 9140753Abstract: A method of validating functional testing of system circuitry on an integrated circuit chip, the system circuitry configured to perform a plurality of functions, the integrated circuit chip further comprising debugging circuitry under the control of a debug controller, the debugging circuitry comprising at least one debug unit. The method comprises: at the system circuitry, performing one of the plurality of functions; applying a debug configuration to the at least one debug unit; and at the at least one debug unit, monitoring for a characteristic in the system circuitry's performance of the one of the plurality of functions according to that debug configuration, and reporting to the debug controller.Type: GrantFiled: April 11, 2014Date of Patent: September 22, 2015Assignee: ULTRASOC TECHNOLOGIES LIMITEDInventors: Andrew Brian Thomas Hopkins, Iain Craig Robertson
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Publication number: 20150226795Abstract: A method of validating functional testing of system circuitry on an integrated circuit chip, the system circuitry configured to perform a plurality of functions, the integrated circuit chip further comprising debugging circuitry under the control of a debug controller, the debugging circuitry comprising at least one debug unit. The method comprises: at the system circuitry, performing one of the plurality of functions; applying a debug configuration to the at least one debug unit; and at the at least one debug unit, monitoring for a characteristic in the system circuitry's performance of the one of the plurality of functions according to that debug configuration, and reporting to the debug controller.Type: ApplicationFiled: April 11, 2014Publication date: August 13, 2015Applicant: UltraSoC Technologies LtdInventors: Andrew Brian Thomas Hopkins, Iain Craig Robertson
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Publication number: 20150226801Abstract: A method of functionality testing system circuitry on an integrated circuit chip, the system circuitry comprising a plurality of sub-circuits and the integrated circuit chip further comprising debugging circuitry, the debugging circuitry comprising variability circuitry. The method comprises: at the system circuitry, performing a function by the sub-circuits performing concurrent actions; at the variability circuitry, altering relative timing of the concurrent actions so as to increase the likelihood of one or more errors in the system circuitry's performance of the function; and at the debugging circuitry, recording one or more errors in the system circuitry's performance of the function.Type: ApplicationFiled: April 11, 2014Publication date: August 13, 2015Applicant: UltraSoC Technologies LtdInventors: Andrew Brian Thomas Hopkins, Iain Craig Robertson, Michael Jonathan Thyer