Patents by Inventor Iain Craig Robertson

Iain Craig Robertson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11095474
    Abstract: A communication device configured to communicate according to a data protocol in which data is carried in packets over a serial data link and the communication device is arranged: to form packets for transmission over the link in such a way that every packet commences with a first bit value; and between transmitting successive packets to continuously transmit a second bit value opposite to the first bit value over the link.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: August 17, 2021
    Assignee: MENTOR GRAPHICS CORPORATION
    Inventors: Andrew Brian Thomas Hopkins, Iain Craig Robertson
  • Patent number: 10437700
    Abstract: A method of tracing transactions on an integrated circuit chip. The method comprises, for each transaction: extracting the transaction from interconnect circuitry of the integrated circuit chip, the transaction comprising an address signal and a data signal; applying a filtering condition to the address signal; only if the address signal does not fail the filtering condition, storing the address signal in an address trace buffer; storing the data signal in a data trace buffer; applying a triggering condition to the stored transaction; and outputting the stored transaction if the stored transaction matches the triggering condition.
    Type: Grant
    Filed: August 19, 2016
    Date of Patent: October 8, 2019
    Assignee: UltraSoC Technologies Limited
    Inventors: Iain Craig Robertson, Andrew Brian Thomas Hopkins, Michael Jonathan Thyer
  • Publication number: 20190273631
    Abstract: A communication device configured to communicate according to a data protocol in which data is carried in packets over a serial data link and the communication device is arranged: to form packets for transmission over the link in such a way that every packet commences with a first bit value; and between transmitting successive packets to continuously transmit a second bit value opposite to the first bit value over the link.
    Type: Application
    Filed: May 16, 2019
    Publication date: September 5, 2019
    Inventors: Andrew Brian Thomas Hopkins, Iain Craig Robertson
  • Patent number: 10326612
    Abstract: A communication device configured to communicate according to a data protocol in which data is carried in packets over a serial data link and the communication device is arranged: to form packets for transmission over the link in such a way that every packet commences with a first bit value; and between transmitting successive packets to continuously transmit a second bit value opposite to the first bit value over the link.
    Type: Grant
    Filed: August 24, 2016
    Date of Patent: June 18, 2019
    Assignee: UltraSoC Technologies Limited
    Inventors: Andrew Brian Thomas Hopkins, Iain Craig Robertson
  • Patent number: 10296476
    Abstract: A method of profiling transactions on an integrated circuit chip. The method comprises, for each transaction: extracting the transaction from interconnect circuitry of the integrated circuit chip; and filtering the transaction at a filtering circuit to determine which passband a parameter of the transaction lies within; sending an increment signal to a counter of a bank of counters, the counter having a counter value indicative of a number of transactions having the parameter lying within the passband; and outputting the counter values of the bank of counters.
    Type: Grant
    Filed: August 12, 2016
    Date of Patent: May 21, 2019
    Assignee: UltraSoC Technologies Limited
    Inventors: Andrew Brian Thomas Hopkins, Michael Jonathan Thyer, Iain Craig Robertson
  • Patent number: 9632138
    Abstract: A method of functionality testing system circuitry on an integrated circuit chip, the system circuitry comprising a plurality of sub-circuits and the integrated circuit chip further comprising debugging circuitry, the debugging circuitry comprising variability circuitry. The method comprises: at the system circuitry, performing a function by the sub-circuits performing concurrent actions; at the variability circuitry, altering relative timing of the concurrent actions so as to increase the likelihood of one or more errors in the system circuitry's performance of the function; and at the debugging circuitry, recording one or more errors in the system circuitry's performance of the function.
    Type: Grant
    Filed: October 9, 2015
    Date of Patent: April 25, 2017
    Assignee: ULTRASOC TECHNOLOGIES LIMITED
    Inventors: Andrew Brian Thomas Hopkins, Iain Craig Robertson, Michael Jonathan Thyer
  • Publication number: 20170063570
    Abstract: A communication device configured to communicate according to a data protocol in which data is carried in packets over a serial data link and the communication device is arranged: to form packets for transmission over the link in such a way that every packet commences with a first bit value; and between transmitting successive packets to continuously transmit a second bit value opposite to the first bit value over the link.
    Type: Application
    Filed: August 24, 2016
    Publication date: March 2, 2017
    Inventors: Andrew Brian Thomas Hopkins, Iain Craig Robertson
  • Publication number: 20170052868
    Abstract: A method of tracing transactions on an integrated circuit chip. The method comprises, for each transaction: extracting the transaction from interconnect circuitry of the integrated circuit chip, the transaction comprising an address signal and a data signal; applying a filtering condition to the address signal; only if the address signal does not fail the filtering condition, storing the address signal in an address trace buffer; storing the data signal in a data trace buffer; applying a triggering condition to the stored transaction; and outputting the stored transaction if the stored transaction matches the triggering condition.
    Type: Application
    Filed: August 19, 2016
    Publication date: February 23, 2017
    Inventors: Iain Craig Robertson, Andrew Brian Thomas Hopkins, Michael Jonathan Thyer
  • Publication number: 20170046288
    Abstract: A method of profiling transactions on an integrated circuit chip. The method comprises, for each transaction: extracting the transaction from interconnect circuitry of the integrated circuit chip; and filtering the transaction at a filtering circuit to determine which passband a parameter of the transaction lies within; sending an increment signal to a counter of a bank of counters, the counter having a counter value indicative of a number of transactions having the parameter lying within the passband; and outputting the counter values of the bank of counters.
    Type: Application
    Filed: August 12, 2016
    Publication date: February 16, 2017
    Inventors: Andrew Brian Thomas Hopkins, Michael Jonathan Thyer, Iain Craig Robertson
  • Patent number: 9424166
    Abstract: An integrated circuit chip device comprising: system circuitry; debugging circuitry configured to debug the system circuitry, the debugging circuitry being segmented into zones; wherein the debugging circuitry comprises an interconnect fabric configured to route debug messages through a zone from a zone entry node of the interconnect fabric to a zone exit node of the interconnect fabric; and wherein the debugging circuitry is configured to, on receiving a debug message at a zone entry node that is shorter than a specified length, modify the debug message to form a modified debug message by increasing the length of the debug message to the specified length.
    Type: Grant
    Filed: April 11, 2014
    Date of Patent: August 23, 2016
    Assignee: ULTRASOC TECHNOLOGIES LIMITED
    Inventors: Andrew Brian Thomas Hopkins, Iain Craig Robertson
  • Publication number: 20160033575
    Abstract: A method of functionality testing system circuitry on an integrated circuit chip, the system circuitry comprising a plurality of sub-circuits and the integrated circuit chip further comprising debugging circuitry, the debugging circuitry comprising variability circuitry. The method comprises: at the system circuitry, performing a function by the sub-circuits performing concurrent actions; at the variability circuitry, altering relative timing of the concurrent actions so as to increase the likelihood of one or more errors in the system circuitry's performance of the function; and at the debugging circuitry, recording one or more errors in the system circuitry's performance of the function.
    Type: Application
    Filed: October 9, 2015
    Publication date: February 4, 2016
    Inventors: Andrew Brian Thomas Hopkins, Iain Craig Robertson, Michael Jonathan Thyer
  • Patent number: 9188638
    Abstract: A method of functionality testing system circuitry on an integrated circuit chip, the system circuitry comprising a plurality of sub-circuits and the integrated circuit chip further comprising debugging circuitry, the debugging circuitry comprising variability circuitry. The method comprises: at the system circuitry, performing a function by the sub-circuits performing concurrent actions; at the variability circuitry, altering relative timing of the concurrent actions so as to increase the likelihood of one or more errors in the system circuitry's performance of the function; and at the debugging circuitry, recording one or more errors in the system circuitry's performance of the function.
    Type: Grant
    Filed: April 11, 2014
    Date of Patent: November 17, 2015
    Assignee: UltraSoC Technologies Ltd.
    Inventors: Andrew Brian Thomas Hopkins, Iain Craig Robertson, Michael Jonathan Thyer
  • Publication number: 20150268302
    Abstract: An integrated circuit chip device comprising: system circuitry; debugging circuitry configured to debug the system circuitry, the debugging circuitry being segmented into zones; wherein the debugging circuitry comprises an interconnect fabric configured to route debug messages through a zone from a zone entry node of the interconnect fabric to a zone exit node of the interconnect fabric; and wherein the debugging circuitry is configured to, on receiving a debug message at a zone entry node that is shorter than a specified length, modify the debug message to form a modified debug message by increasing the length of the debug message to the specified length.
    Type: Application
    Filed: April 11, 2014
    Publication date: September 24, 2015
    Inventors: Andrew Brian Thomas Hopkins, Iain Craig Robertson
  • Patent number: 9140753
    Abstract: A method of validating functional testing of system circuitry on an integrated circuit chip, the system circuitry configured to perform a plurality of functions, the integrated circuit chip further comprising debugging circuitry under the control of a debug controller, the debugging circuitry comprising at least one debug unit. The method comprises: at the system circuitry, performing one of the plurality of functions; applying a debug configuration to the at least one debug unit; and at the at least one debug unit, monitoring for a characteristic in the system circuitry's performance of the one of the plurality of functions according to that debug configuration, and reporting to the debug controller.
    Type: Grant
    Filed: April 11, 2014
    Date of Patent: September 22, 2015
    Assignee: ULTRASOC TECHNOLOGIES LIMITED
    Inventors: Andrew Brian Thomas Hopkins, Iain Craig Robertson
  • Publication number: 20150226795
    Abstract: A method of validating functional testing of system circuitry on an integrated circuit chip, the system circuitry configured to perform a plurality of functions, the integrated circuit chip further comprising debugging circuitry under the control of a debug controller, the debugging circuitry comprising at least one debug unit. The method comprises: at the system circuitry, performing one of the plurality of functions; applying a debug configuration to the at least one debug unit; and at the at least one debug unit, monitoring for a characteristic in the system circuitry's performance of the one of the plurality of functions according to that debug configuration, and reporting to the debug controller.
    Type: Application
    Filed: April 11, 2014
    Publication date: August 13, 2015
    Applicant: UltraSoC Technologies Ltd
    Inventors: Andrew Brian Thomas Hopkins, Iain Craig Robertson
  • Publication number: 20150226801
    Abstract: A method of functionality testing system circuitry on an integrated circuit chip, the system circuitry comprising a plurality of sub-circuits and the integrated circuit chip further comprising debugging circuitry, the debugging circuitry comprising variability circuitry. The method comprises: at the system circuitry, performing a function by the sub-circuits performing concurrent actions; at the variability circuitry, altering relative timing of the concurrent actions so as to increase the likelihood of one or more errors in the system circuitry's performance of the function; and at the debugging circuitry, recording one or more errors in the system circuitry's performance of the function.
    Type: Application
    Filed: April 11, 2014
    Publication date: August 13, 2015
    Applicant: UltraSoC Technologies Ltd
    Inventors: Andrew Brian Thomas Hopkins, Iain Craig Robertson, Michael Jonathan Thyer