Patents by Inventor Ian Andrew Swarbrick
Ian Andrew Swarbrick has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11263169Abstract: An example programmable integrated circuit (IC) includes a processor, a plurality of endpoint circuits, a network-on-chip (NoC) having NoC master units (NMUs), NoC slave units (NSUs), NoC programmable switches (NPSs), a plurality of registers, and a NoC programming interface (NPI). The processor is coupled to the NPI and is configured to program the NPSs by loading an image to the registers through the NPI for providing physical channels between NMUs to the NSUs and providing data paths between the plurality of endpoint circuits.Type: GrantFiled: November 16, 2020Date of Patent: March 1, 2022Assignee: XILINX, INC.Inventors: Ian Andrew Swarbrick, Sagheer Ahmad, Ygal Arbel, Dinesh Gaitonde
-
Publication number: 20210303509Abstract: An example programmable integrated circuit (IC) includes a processor, a plurality of endpoint circuits, a network-on-chip (NoC) having NoC master units (NMUs), NoC slave units (NSUs), NoC programmable switches (NPSs), a plurality of registers, and a NoC programming interface (NPI). The processor is coupled to the NPI and is configured to program the NPSs by loading an image to the registers through the NPI for providing physical channels between NMUs to the NSUs and providing data paths between the plurality of endpoint circuits.Type: ApplicationFiled: November 16, 2020Publication date: September 30, 2021Inventors: Ian Andrew SWARBRICK, Sagheer AHMAD, Ygal ARBEL, Dinesh GAITONDE
-
Patent number: 10062422Abstract: An interconnect for an integrated circuit communicating transactions between initiator Intellectual Property (IP) cores and multiple target IP cores coupled to the interconnect is generally described. The interconnect routes the transactions between the target IP cores and initiator IP cores in the integrated circuit. A first aggregate target of the target IP cores includes two or more memory channels that are interleaved in an address space for the first aggregate target in the address map. Each memory channel is divided up in defined memory interleave segments and then interleaved with memory interleave segments from other memory channels. An address map is divided up into two or more regions. Each interleaved memory interleave segment is assigned to at least one of those regions and populates the address space for that region, and parameters associated with the regions and memory interleave segments are configurable.Type: GrantFiled: November 23, 2016Date of Patent: August 28, 2018Assignee: Sonics, Inc.Inventors: Drew E. Wingard, Chien-Chun Chou, Stephen W. Hamilton, Ian Andrew Swarbrick, Vida Vakilotojar
-
Publication number: 20170140800Abstract: An interconnect for an integrated circuit communicating transactions between initiator Intellectual Property (IP) cores and multiple target IP cores coupled to the interconnect is generally described. The interconnect routes the transactions between the target IP cores and initiator IP cores in the integrated circuit. A first aggregate target of the target IP cores includes two or more memory channels that are interleaved in an address space for the first aggregate target in the address map. Each memory channel is divided up in defined memory interleave segments and then interleaved with memory interleave segments from other memory channels. An address map is divided up into two or more regions. Each interleaved memory interleave segment is assigned to at least one of those regions and populates the address space for that region, and parameters associated with the regions and memory interleave segments are configurable.Type: ApplicationFiled: November 23, 2016Publication date: May 18, 2017Applicant: Sonics, Inc.Inventors: Drew E. Wingard, Chien-Chun Chou, Stephen W. Hamilton, Ian Andrew Swarbrick, Vida Vakilotojar
-
Patent number: 9495290Abstract: A method, apparatus, and system are described, which generally relate to an integrated circuit having an interconnect that implements internal controls. The interconnect in an integrated circuit communicates transactions between initiator Intellectual Property (IP) cores and target IP cores coupled to the interconnect. The interconnect implements logic configured to support multiple transactions issued from a first initiator IP core to the multiple target IP cores while maintaining an expected execution order within the transactions. The logic supports a second transaction to be issued from the first initiator IP core to a second target IP core before a first transaction issued from the same first initiator IP core to a first target IP core has completed while ensuring that the first transaction completes before the second transaction and while ensuring an expected execution order within the first transaction and second transaction are maintained. The logic does not include any reorder buffering.Type: GrantFiled: June 24, 2008Date of Patent: November 15, 2016Assignee: Sonics, Inc.Inventors: Drew E. Wingard, Chien-Chun Chou, Stephen W. Hamilton, Ian Andrew Swarbrick, Vida Vakilotojar
-
Patent number: 9292436Abstract: A method, apparatus, and system are described, which generally relate to an interconnect routing transactions to target IP cores, including two or more channels making up a first aggregate target. The two or more channels populate an address space assigned to the first aggregate target and appear as a single target to the initiator IP cores. The interconnect implements chopping logic to chop an individual transaction from a first initiator IP core whose address sequence crosses a channel address boundary from a first channel to a second channel within the first aggregate target into two or more burst transactions. A first chopped burst transaction is chopped to fit within the address boundaries of the first channel and a second chopped burst transaction is chopped to fit within the address boundaries of the second channel.Type: GrantFiled: June 24, 2008Date of Patent: March 22, 2016Assignee: Sonics, Inc.Inventors: Drew E. Wingard, Chien-Chun Chou, Stephen W. Hamilton, Ian Andrew Swarbrick, Vida Vakilotojar
-
Patent number: 8407433Abstract: In an embodiment, an interconnect for an integrated circuit communicates transactions between one or more initiator Intellectual Property (IP) cores and multiple target IP cores coupled to the interconnect. Two or more memory channels make up a first aggregate target of the target IP cores. The two or more memory channels populate an address space assigned to the first aggregate target and appear as a single target to the initiator IP cores. The interconnect implements chopping logic to chop individual two-dimensional (2D) transactions that cross the memory channel address boundaries from a first memory channel to a second memory channel within the first aggregate target into two or more 2D transactions with a height value greater than one, as well as stride and width dimensions, which are chopped to fit within memory channel address boundaries of the first aggregate target.Type: GrantFiled: June 24, 2008Date of Patent: March 26, 2013Assignee: Sonics, Inc.Inventors: Drew E. Wingard, Chien-Chun Chou, Stephen W. Hamilton, Ian Andrew Swarbrick, Vida Vakilotojar
-
Publication number: 20120036296Abstract: A method, apparatus, and system are described, which generally relate to an integrated circuit having an interconnect. The flow control logic for the interconnect applies a flow control splitting protocol to permit transactions from each initiator thread and/or each initiator tag stream to be outstanding to multiple channels in a single aggregate target at once, and therefore to multiple individual targets within an aggregate target at once. The combined flow control logic and flow control protocol allows the interconnect to manage simultaneous requests to multiple channels in an aggregate target from the same thread or tag at the same time.Type: ApplicationFiled: October 18, 2011Publication date: February 9, 2012Applicant: SONICS, INC.Inventors: Drew E. Wingard, Chien-Chun Chou, Stephen W. Hamilton, Ian Andrew Swarbrick, Vida Vakilotojar
-
Patent number: 8024697Abstract: Methods and apparatuses are described for an Intellectual Property (IP) Generator for estimating timing, area, and power characteristics of an electronic system design. The IP Generator receives a user-supplied file having data describing a configuration of an IP design having multiple levels of hierarchy. The IP Generator also receives user-supplied technology parameters and data-flow information. The IP generator correlates estimated timing, area, and power characteristics for each IP sub component based on the user supplied technology parameters, data-flow information and configuration parameters. The IP generator reports the timing, area, and power estimates to a user via a graphic user interface prior to a transformation of a Register Transfer Level (RTL) design into the gate-level circuit design.Type: GrantFiled: March 23, 2010Date of Patent: September 20, 2011Assignee: Sonics, Inc.Inventors: Stephen Hamilton, Ian Andrew Swarbrick, Scott Carlton Evans, Wolf-Dietrich Weber, Jay S. Tomlinson
-
Publication number: 20100318946Abstract: Methods and apparatuses are described for an Intellectual Property (IP) Generator for estimating timing, area, and power characteristics of an electronic system design. The IP Generator receives a user-supplied file having data describing a configuration of an IP design having multiple levels of hierarchy. The IP Generator also receives user-supplied technology parameters and data-flow information. The IP generator correlates estimated timing, area, and power characteristics for each IP sub component based on the user supplied technology parameters, data-flow information and configuration parameters. The IP generator reports the timing, area, and power estimates to a user via a graphic user interface prior to a transformation of a Register Transfer Level (RTL) design into the gate-level circuit design.Type: ApplicationFiled: March 23, 2010Publication date: December 16, 2010Applicant: Sonics, Inc.Inventors: Stephen Hamilton, Ian Andrew Swarbrick, Scott Carlton Evans, Wolf-Dietrich Weber, Jay S. Tomlinson
-
Patent number: 7694249Abstract: Methods and apparatuses are described for an Intellectual Property (IP) Generator for estimating timing, area, and power characteristics of an electronic system design. The IP Generator receives a user-supplied file having data describing a configuration of an IP design having multiple levels of hierarchy. The IP Generator also receives user-supplied technology parameters and data-flow information. The IP generator correlates estimated timing, area, and power characteristics for each IP sub component based on the user supplied technology parameters, data-flow information and configuration parameters. The IP generator reports the timing, area, and power estimates to a user via a graphic user interface prior to a transformation of a Register Transfer Level (RTL) design into the gate-level circuit design.Type: GrantFiled: April 4, 2006Date of Patent: April 6, 2010Assignee: Sonics, Inc.Inventors: Stephen Hamilton, Ian Andrew Swarbrick, Scott Carlton Evans, Wolf-Dietrich Weber, Jay S. Tomlinson
-
Publication number: 20080320268Abstract: In an embodiment, an interconnect for an integrated circuit communicates transactions between one or more initiator Intellectual Property (IP) cores and multiple target IP cores coupled to the interconnect. Two or more memory channels make up a first aggregate target of the target IP cores. The two or more memory channels populate an address space assigned to the first aggregate target and appear as a single target to the initiator IP cores. The interconnect implements chopping logic to chop individual two-dimensional (2D) transactions that cross the memory channel address boundaries from a first memory channel to a second memory channel within the first aggregate target into two or more 2D transactions with a height value greater than one, as well as stride and width dimensions, which are chopped to fit within memory channel address boundaries of the first aggregate target.Type: ApplicationFiled: June 24, 2008Publication date: December 25, 2008Applicant: Sonics, Inc.Inventors: Drew E. Wingard, Chien-Chun Chou, Ian Andrew Swarbrick, Stephen W. Hamilton, Vida Vakilotojar
-
Publication number: 20080320254Abstract: A method, apparatus, and system are described, which generally relate to an interconnect routing transactions to target IP cores, including two or more channels making up a first aggregate target. The two or more channels populate an address space assigned to the first aggregate target and appear as a single target to the initiator IP cores. The interconnect implements chopping logic to chop an individual transaction from a first initiator IP core whose address sequence crosses a channel address boundary from a first channel to a second channel within the first aggregate target into two or more burst transactions. A first chopped burst transaction is chopped to fit within the address boundaries of the first channel and a second chopped burst transaction is chopped to fit within the address boundaries of the second channel.Type: ApplicationFiled: June 24, 2008Publication date: December 25, 2008Applicant: Sonics, Inc.Inventors: Drew E. Wingard, Chien-Chun Chou, Stephen W. Hamilton, Ian Andrew Swarbrick, Vida Vakilotojar
-
Publication number: 20080320476Abstract: A method, apparatus, and system are described, which generally relate to an integrated circuit having an interconnect that implements internal controls. The interconnect in an integrated circuit communicates transactions between initiator Intellectual Property (IP) cores and target IP cores coupled to the interconnect. The interconnect implements logic configured to support multiple transactions issued from a first initiator IP core to the multiple target IP cores while maintaining an expected execution order within the transactions. The logic supports a second transaction to be issued from the first initiator IP core to a second target IP core before a first transaction issued from the same first initiator IP core to a first target IP core has completed while ensuring that the first transaction completes before the second transaction and while ensuring an expected execution order within the first transaction and second transaction are maintained. The logic does not include any reorder buffering.Type: ApplicationFiled: June 24, 2008Publication date: December 25, 2008Applicant: Sonics, Inc.Inventors: Drew E. Wingard, Chien-Chun Chou, Stephen W. Hamilton, Ian Andrew Swarbrick, Vida Vakilotojar
-
Publication number: 20080320255Abstract: An interconnect for an integrated circuit communicating transactions between initiator Intellectual Property (IP) cores and multiple target IP cores coupled to the interconnect is generally described. The interconnect routes the transactions between the target IP cores and initiator IP cores in the integrated circuit. A first aggregate target of the target IP cores includes two or more memory channels that are interleaved in an address space for the first aggregate target in the address map. Each memory channel is divided up in defined memory interleave segments and then interleaved with memory interleave segments from other memory channels. An address map is divided up into two or more regions. Each interleaved memory interleave segment is assigned to at least one of those regions and populates the address space for that region, and parameters associated with the regions and memory interleave segments are configurable.Type: ApplicationFiled: June 24, 2008Publication date: December 25, 2008Applicant: Sonics, Inc.Inventors: Drew E. Wingard, Chien-Chun Chou, Stephen W. Hamilton, Ian Andrew Swarbrick, Vida Vakilotojar
-
Patent number: 7149829Abstract: Various methods and apparatuses are described in which an arbitration controller cooperates with arbitration logic. The arbitration controller has a plurality of inputs that receive one or more transactions from a plurality of blocks of functionality. The arbitration controller arbitrates requests for access to a shared resource amongst the plurality of blocks of functionality by implementing an arbitration policy. The arbitration policy groups the transactions from the plurality of blocks of functionality into global groups of transactions for servicing by that shared resource. All of the transactions in a first global group are serviced by that shared resource prior to servicing transactions in a next global group of transactions. The arbitration logic facilitates the arbitration policy. The arbitration logic includes cascaded arbitration units that hierarchically arbitrate for the shared resource.Type: GrantFiled: April 18, 2003Date of Patent: December 12, 2006Assignee: Sonics, Inc.Inventors: Wolf-Dietrich Weber, Ian Andrew Swarbrick, Jay S. Tomlinson
-
Publication number: 20040210695Abstract: Various methods and apparatuses are described in which an arbitration controller cooperates with arbitration logic. The arbitration controller has a plurality of inputs that receive one or more transactions from a plurality of blocks of functionality. The arbitration controller arbitrates requests for access to a shared resource amongst the plurality of blocks of functionality by implementing an arbitration policy. The arbitration policy groups the transactions from the plurality of blocks of functionality into global groups of transactions for servicing by that shared resource. All of the transactions in a first global group are serviced by that shared resource prior to servicing transactions in a next global group of transactions. The arbitration logic facilitates the arbitration policy. The arbitration logic includes cascaded arbitration units that hierarchically arbitrate for the shared resource.Type: ApplicationFiled: April 18, 2003Publication date: October 21, 2004Inventors: Wolf-Dietrich Weber, Ian Andrew Swarbrick, Jay S. Tomlinson