Abstract: Methods and apparatus to generate and display trends associated with a process control system are disclosed. An example apparatus includes memory, machine readable instructions, and processor circuitry to execute the instructions to generate a first graphical user interface. The first graphical user interface to include a graphical representation of a component in a process control system. The processor circuitry to generate a second graphical user interface. The second graphical user interface to include a chart region with a trend represented therein. The trend indicative of values of a process parameter of the process control system over a period of time. The processor circuitry to automatically generate the trend in the chart region in response to a graphical element being dragged and dropped from the first graphical user interface to the second graphical user interface.

Abstract: Multi-semiconductor SSPCs that solve bus level problems affecting systems as well as controller level problems affecting individual multi-semiconductor SSPCs are disclosed. Bus level and controller level problems adversely affect multi-semiconductor SSPCs and their associated systems. The disclosed multi-semiconductor SSPCs solve both bus level and controller level problems by implementing controlled rate-change of voltage (dv/dt) ramp-on rate, to ensure that the voltage on the input bus does not collapse when a multi-semiconductor SSPC is commanded closed and that a minimum amount of power is being dissipated evenly across the switching semiconductors.

Abstract: A switch for connection in a network of other like switches and includes memory for storing data packets, a control system arranged to control the switch to, upon receipt at one of the ingress or egress ports of notification of congestion at a downstream congested port, either store at said ingress port or egress port data packets received for said congested port or to communicate with an upstream port for storage at said upstream port of data packets destined for the congested port, and in dependence on the current of stored data, to send a message to a further upstream port informing the further upstream port of the congestion downstream. The memory is provided substantially only at the ingress ports or the egress ports of the switch.

Abstract: A method of congestion management within a switch or network of connected switches is provided, wherein the or each of the switches has a plurality of ingress ports and a plurality of egress ports. The method involves, when congestion is detected at a first ingress or egress port, sending a message to an upstream port connected to the first ingress or egress port indicating that congestion has occurred at a particular port and requesting storage at the upstream port of data packets destined for that port; and, in dependence on the amount of data packets destined for the congested port stored at the upstream port, sending from the upstream port to a further upstream port a message informing the further upstream port of the congestion at the congested port, the further upstream port storing at the further upstream port data packets destined for the congested port.

Abstract: The invention provides a method of manufacturing an optical printed circuit board and an optical printed circuit board. The method comprises providing a support layer; on the support layer, providing an optical core layer; forming optical channels from the optical core layer and surrounding the optical channels with cladding thereby forming optical waveguides; and during said step of forming the optical channels, forming one or more alignment features, e.g. projections, on the optical printed circuit board.

Abstract: The invention provides a method of manufacturing an optical printed circuit board and an optical printed circuit board. The method comprises providing a support layer; on the support layer, providing an optical core layer; forming optical channels from the optical core layer and surrounding the optical channels with cladding thereby forming optical waveguides; and during said step of forming the optical channels, forming one or more alignment features, e.g. projections, on the optical printed circuit board.

Abstract: A switch for connection in a network of other like switches and includes memory for storing data packets, a control system arranged to control the switch to, upon receipt at one of the ingress or egress ports of notification of congestion at a downstream congested port, either store at said ingress port or egress port data packets received for said congested port or to communicate with an upstream port for storage at said upstream port of data packets destined for the congested port, and in dependence on the current of stored data, to send a message to a further upstream port informing the further upstream port of the congestion downstream. The memory is provided substantially only at the ingress ports or the egress ports of the switch.

Abstract: The present invention relates to a switch and a method of switching for switching data frames. The switch comprises plural input ports and plural output ports; a central switch fabric configurable in any switching cycle to make connections between required pairs of the input ports and output ports; one or more transmit devices configured to receive data from the input ports and transmit data cells across the switch fabric; a controller for controlling the operation of the transmit devices, the plural input ports and output ports and the switch fabric; and multicast storage associated with the or each of the transmit devices for storage of fragmenting multicast cells and onward transmission of the fragmented cells.

Abstract: The invention relates to a data switch, comprising: plural input ports each for receiving data cells from a respective link; plural output ports each for providing data cells to a respective link; a switch fabric for selectively enabling a data cell received at one of the plural input ports to be switched to one or more of the plural output ports; and a switch scheduler comprising a cut-through arbiter arranged to schedule the switching of a received data cell before the entirety of the data cell is received.

Abstract: A method of congestion management within a switch or network of connected switches is provided, wherein the or each of the switches has a plurality of ingress ports and a plurality of egress ports. The method involves, when congestion is detected at a first ingress or egress port, sending a message to an upstream port connected to the first ingress or egress port indicating that congestion has occurred at a particular port and requesting storage at the upstream port of data packets destined for that port; and, in dependence on the amount of data packets destined for the congested port stored at the upstream port, sending from the upstream port to a further upstream port a message informing the further upstream port of the congestion at the congested port, the further upstream port storing at the further upstream port data packets destined for the congested port.

Abstract: According to the present invention there is provided a scheduling and arbitration process for use in a digital data switching arrangement of the type in which a central switch under the direction of a master control provides the cross-connections between a number of high-bandwidth ports to which are connected on the ingress side of the central switch a number of ingress multiplexers, one for each high-bandwidth input port and on the egress side a number of egress multiplexers, one for each high-bandwidth output port, each ingress multiplexer including a set of N input queues serving N low-bandwidth data sources and a set of M virtual output queues serving M low-bandwidth output data sources, characterized in that the scheduling and arbitration arrangement includes three bandwidth allocation tables, an ingress port table associated with the input queues and having N×M entries each arranged to define the bandwidth for a particular virtual output queue, an egress port table associated with the virtual output que

Abstract: A data switch for handling packets of information; the switch includes input traffic managers, ingress routers, a memoryless cyclic switch fabric, egress routers and output traffic managers all acting under the control of a switch controller. Each ingress router includes a set of virtual output buffers one for each output traffic manager and each message priority. Each data packet or cell as it arrives is examined to identify the output traffic manager address and its message priority. The switch controller uses a first arbitration and selection process to schedule the passage of the next cell across the switch fabric which the ingress router uses a second arbitration and selection process to select the appropriate virtual output queue for use in the switch fabric transfer.

Abstract: There is disclosed a masking unit (REQMSK) for use in a data packet switching system. The data switching system being of the type having a memoryless cross-back switch (SM) providing cyclic connections under the control of a switch arbiter (SCARB) between ingress routers (IR0, IR1, IR2 and IR3) and egress routers (ER0, ER1, ER2 and ER3). Each of the ingress routers (IR0–IR3) is provided with incoming packet buffering on a virtual output queue basis (VOQ0.0, VOQ0.1, VOQ0.2, and VOQ0.3 for ingress router IR0). Each virtual output queue also produces a connection request signal REQ0.0 to REQ3.3 when the corresponding queue has a data packet in it. The masking unit REQMSK is arranged to randomly mask out correlated connection requests.

Abstract: In a data switching system, the ingress and egress ports of a memoryless cross-bar switch are controlled by an arbitration method. The arbitration method uses a three phase process involving (i) a request phase in which each ingress port sends its connection requests to egress ports to which a connection is required, (ii) a grant phase in which each egress port uses a grant pointer to select one of the requests directed to it using a grant pointer, and generates a grant signal, and (iii) an accept phase in which each ingress port selects one of the received grant signals to accept, so defining an ingress to egress port connection across the cross-bar switch. The transition sequences for each of the grant pointers are mutually exclusive, so that any synchronisation of the grant pointers is eliminated on the next arbitration cycle. This is arranged by a setting of the paths taken by request and grant signals.

Abstract: A scheduling means for data switching apparatus includes a plurality of input ports and a plurality of output ports, the scheduling means capable of processing a plurality of interconnection requests, each requesting interconnection between a sub-set of the input ports and a sub-set of respective the output ports, and each request having a respective priority level which is one of a predetermined number of priority levels.

Abstract: An arbitration process sets the connections to be made between ingress and egress ports of a crossbar switch of a data switching system. A weight parameter is used for each pair of ingress and egress ports. Connection requests are generated indicating ingress ports to be connected to egress ports. A selection is made among conflicting connection requests, to produce a connection proposal for each egress port. Any connection request for which respective weighting parameter is zero is not selected. When one of the connection requests is realised, the weight parameter corresponding to this connection is decreased by one. All the weight parameters for a given egress port are re-set to default values in the case that there are no connection requests for that egress port with non-zero weights.

Abstract: A data switching device has ingress routers and egress routers interconnected by a switching matrix controlled by a controller. Each ingress router maintains one or more virtual output queues for each egress router. The switching matrix itself maintains a head-of queue buffer of cells which are to be transmitted. Each of these queues corresponds to one of the virtual output queues, and the cells stored in the switching matrix are replicated from the cells queuing in the respective virtual output queues. Thus, when it is determined that a connection is to be made between a given input and output of the switching matrix, a cell suitable for transmission along that connection is already available to the switching matrix. Upon receipt of a new cell by one of the ingress routers, the cell is stored in one of the virtual output queues of the ingress router corresponding to the egress router for the cell, and also written the corresponding head of queue buffer, if that buffer has space.

Abstract: A data packet switching system having a central controller and a number of peripheral controllers each incorporating at least one queue for storing packets of information received from a peripheral data packet source. Each queue in each peripheral controller includes a queue size detection logic adapted to communicate to the central controller the approximate state of the size of the corresponding queue. The scale for the approximate state being arranged to be empty, nearly empty, active, busy, very busy, nearly full and full.

Abstract: A method of operating a RAM memory having a plurality of memory addresses for storing data, the method being performed with a timing based on clock signals spaced by clock periods and comprising the steps of: receiving an address and a function signal specifying a function to be performed on data associated with that address; determining whether the same address has been received during a predefined number of preceding clock periods; generating a first data item representing data associated with the received address; modifying the first item according to the function signal to generate a second data item associated with the address, and writing the second data item to the address in the RAM and retaining a separate record of the last n second data items, the step of generating a first data item being performed by: (i) if the result of the determination is negative, generating the first data item to be equal to data stored by the RAM in the address, and (ii) if the result of the determination is positive, gene

Abstract: A synchronizing arrangement for a closed-loop data transmission system includes a central data switch and a plurality of transceivers which may be interconnected by way of the switch for the transmission of data between them. The central data switch includes a clock generator, and a plurality of ports, each of which includes a transmitter, a receiver, a phase detector and a phase encoder. Each transceiver includes a data transmitter, a data receiver and a synchronizing means operable to maintain synchronism between the transceiver and the data port. A common reference oscillator provides frequency reference signals to the central data switch, each data port and each transceiver.