Patents by Inventor Ian E. Davis
Ian E. Davis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 10348631Abstract: Methods and systems for load balancing are disclosed. An example method for load balancing commences with receiving a data packet from a host device. The method further includes identifying a header field of the data packet. After identifying the header field of the data packet, the method proceeds with matching the data packet to a network service based on the header field. Thereafter, the method generates a header field block for the data packet based on the network service. The method further includes sending the data packet to a processor module. The data packet is processed based on the header field block.Type: GrantFiled: November 16, 2017Date of Patent: July 9, 2019Assignee: A10 Networks, Inc.Inventors: Gurudeep Kamat, Ian E. Davis, Rajkumar Jalan
-
Patent number: 10069946Abstract: Hardware-based packet editor receives a packet editing script which includes script entries indicating modifications to a data packet and a data block with data for the modified data packet. For a script entry in the packet editing script, the packet editor copies data in the data block at a block location and with a block length identified in the script entry into a packet buffer. The packet editor repeats the copying for the remaining script entries for the modified data packet. The packet editor then generates the modified data packet with the data in the packet buffer. The packet editing script is generated such that a script entry is created for data to be included in the modified data packet and data to be inserted into the modified data packet. Creation of a script entry is omitted for data to be removed.Type: GrantFiled: July 26, 2017Date of Patent: September 4, 2018Assignee: A10 NETWORKS, INC.Inventor: Ian E. Davis
-
Publication number: 20180091429Abstract: Methods and systems for load balancing are disclosed. An example method for load balancing commences with receiving a data packet from a host device. The method further includes identifying a header field of the data packet. After identifying the header field of the data packet, the method proceeds with matching the data packet to a network service based on the header field. Thereafter, the method generates a header field block for the data packet based on the network service. The method further includes sending the data packet to a processor module. The data packet is processed based on the header field block.Type: ApplicationFiled: November 16, 2017Publication date: March 29, 2018Inventors: Gurudeep Kamat, Ian E. Davis, Rajkumar Jalan
-
Patent number: 9843521Abstract: In processing data packet headers, a packet pre-processor is configured with at least one predetermined header field identifier. The packet pre-processor detects at least one header field identifier in a header field of a data packet received over a communication session between a host and a server, matches the predetermined header field identifier to the header field identifier in the data packet, generates a header report block comprising information corresponding to the header field identifier in the data packet, and sends the data packet and the header report block to a processor module for processing the data packet based on the header report block. The processor module receives the data packet and the header report block from the packet pre-processor, retrieves a service policy using the header report block, applies the service policy to the data packet, and sends the data packet to the host or the server.Type: GrantFiled: March 13, 2017Date of Patent: December 12, 2017Assignee: A10 NETWORKS, INC.Inventors: Gurudeep Kamat, Ian E. Davis, Rajkumar Jalan
-
Publication number: 20170324846Abstract: Hardware-based packet editor receives a packet editing script which includes script entries indicating modifications to a data packet and a data block with data for the modified data packet. For a script entry in the packet editing script, the packet editor copies data in the data block at a block location and with a block length identified in the script entry into a packet buffer. The packet editor repeats the copying for the remaining script entries for the modified data packet. The packet editor then generates the modified data packet with the data in the packet buffer. The packet editing script is generated such that a script entry is created for data to be included in the modified data packet and data to be inserted into the modified data packet. Creation of a script entry is omitted for data to be removed.Type: ApplicationFiled: July 26, 2017Publication date: November 9, 2017Inventor: Ian E. Davis
-
Patent number: 9742879Abstract: Hardware-based packet editor receives a packet editing script which includes script entries indicating modifications to a data packet and a data block with data for the modified data packet. For a script entry in the packet editing script, the packet editor copies data in the data block at a block location and with a block length identified in the script entry into a packet buffer. The packet editor repeats the copying for the remaining script entries for the modified data packet. The packet editor then generates the modified data packet with the data in the packet buffer. The packet editing script is generated such that a script entry is created for data to be included in the modified data packet and data to be inserted into the modified data packet. Creation of a script entry is omitted for data to be removed.Type: GrantFiled: August 13, 2015Date of Patent: August 22, 2017Assignee: A10 NETWORKS, INC.Inventor: Ian E. Davis
-
Publication number: 20170187631Abstract: In processing data packet headers, a packet pre-processor is configured with at least one predetermined header field identifier. The packet pre-processor detects at least one header field identifier in a header field of a data packet received over a communication session between a host and a server, matches the predetermined header field identifier to the header field identifier in the data packet, generates a header report block comprising information corresponding to the header field identifier in the data packet, and sends the data packet and the header report block to a processor module for processing the data packet based on the header report block. The processor module receives the data packet and the header report block from the packet pre-processor, retrieves a service policy using the header report block, applies the service policy to the data packet, and sends the data packet to the host or the server.Type: ApplicationFiled: March 13, 2017Publication date: June 29, 2017Inventors: Gurudeep Kamat, Ian E. Davis, Rajkumar Jalan
-
Patent number: 9596286Abstract: In processing Hypertext Transfer Protocol (HTTP) headers, a packet pre-processor is configured with at least one predetermined header field identifier. The packet pre-processor detects at least one header field identifier in a header field of an HTTP packet received over an HTTP session between a host and a server, matches the predetermined header field identifier to the header field identifier in the HTTP packet, generates a header report block comprising information corresponding to the header field identifier in the HTTP packet, and sends the HTTP packet and the header report block to a processor module for processing the HTTP packet based on the header report block. The processor module receives the HTTP packet and the header report block from the packet pre-processor, retrieves a service policy using the header report block, applies the service policy to the HTTP packet, and sends the HTTP packet to the host or the server.Type: GrantFiled: May 25, 2012Date of Patent: March 14, 2017Assignee: A10 Networks, Inc.Inventors: Gurudeep Kamat, Ian E. Davis, Rajkumar Jalan
-
Publication number: 20150350383Abstract: Hardware-based packet editor receives a packet editing script which includes script entries indicating modifications to a data packet and a data block with data for the modified data packet. For a script entry in the packet editing script, the packet editor copies data in the data block at a block location and with a block length identified in the script entry into a packet buffer. The packet editor repeats the copying for the remaining script entries for the modified data packet. The packet editor then generates the modified data packet with the data in the packet buffer. The packet editing script is generated such that a script entry is created for data to be included in the modified data packet and data to be inserted into the modified data packet. Creation of a script entry is omitted for data to be removed.Type: ApplicationFiled: August 13, 2015Publication date: December 3, 2015Inventor: Ian E. Davis
-
Patent number: 9118620Abstract: Hardware-based packet editor receives a packet editing script which includes script entries indicating modifications to a data packet and a data block with data for the modified data packet. For a script entry in the packet editing script, the packet editor copies data in the data block at a block location and with a block length identified in the script entry into a packet buffer. The packet editor repeats the copying for the remaining script entries for the modified data packet. The packet editor then generates the modified data packet with the data in the packet buffer. The packet editing script is generated such that a script entry is created for data to be included in the modified data packet and data to be inserted into the modified data packet. Creation of a script entry is omitted for data to be removed.Type: GrantFiled: June 20, 2012Date of Patent: August 25, 2015Assignee: A10 Networks, Inc.Inventor: Ian E. Davis
-
Patent number: 9118618Abstract: Hardware-based packet editor receives a packet editing script which includes script entries indicating modifications to a data packet and a data block with data for the modified data packet. For a script entry in the packet editing script, the packet editor copies data in the data block at a block location and with a block length identified in the script entry into a packet buffer. The packet editor repeats the copying for the remaining script entries for the modified data packet. The packet editor then generates the modified data packet with the data in the packet buffer. The packet editing script is generated such that a script entry is created for data to be included in the modified data packet and data to be inserted into the modified data packet. Creation of a script entry is omitted for data to be removed.Type: GrantFiled: March 29, 2012Date of Patent: August 25, 2015Assignee: A10 Networks, Inc.Inventor: Ian E. Davis
-
Publication number: 20130315241Abstract: In processing Hypertext Transfer Protocol (HTTP) headers, a packet pre-processor is configured with at least one predetermined header field identifier. The packet pre-processor detects at least one header field identifier in a header field of an HTTP packet received over an HTTP session between a host and a server, matches the predetermined header field identifier to the header field identifier in the HTTP packet, generates a header report block comprising information corresponding to the header field identifier in the HTTP packet, and sends the HTTP packet and the header report block to a processor module for processing the HTTP packet based on the header report block. The processor module receives the HTTP packet and the header report block from the packet pre-processor, retrieves a service policy using the header report block, applies the service policy to the HTTP packet, and sends the HTTP packet to the host or the server.Type: ApplicationFiled: May 25, 2012Publication date: November 28, 2013Applicant: A10 NETWORKS, INC.Inventors: Gurudeep KAMAT, Ian E. DAVIS, Rajkumar JALAN
-
Publication number: 20130262702Abstract: Hardware-based packet editor receives a packet editing script which includes script entries indicating modifications to a data packet and a data block with data for the modified data packet. For a script entry in the packet editing script, the packet editor copies data in the data block at a block location and with a block length identified in the script entry into a packet buffer. The packet editor repeats the copying for the remaining script entries for the modified data packet. The packet editor then generates the modified data packet with the data in the packet buffer. The packet editing script is generated such that a script entry is created for data to be included in the modified data packet and data to be inserted into the modified data packet. Creation of a script entry is omitted for data to be removed.Type: ApplicationFiled: March 29, 2012Publication date: October 3, 2013Applicant: A10 NETWORKS, INC.Inventor: Ian E. DAVIS
-
Patent number: 5901322Abstract: A method and apparatus are provided for controlling clocks for a processor and L2 cache. The clock signal to an L2 cache may be shut down in order to conserve power. Due to the nature of CMOS circuitry typically comprising the SRAM in an L2 cache, shutting down the clock signal to the L2 cache may significantly reduce the amount of power consumed by the L2 cache. A clock control circuitry may be provided to generate and control clock signals to a processor (e.g., Pentium.RTM. processor) and an L2 cache. Controllable clock skew adjustment may be provided to adjust relative timing between clock signals. Skew adjustment for the L2 cache clock may be provided with an AND gate for interrupting the clock signal. The AND gate may be controlled by one of a number of signals indicating status of the L2 cache. Address strobe, L2 idle, or pipelining conditions may determine whether the clock signal to the L2 cache may be interrupted.Type: GrantFiled: August 8, 1997Date of Patent: May 4, 1999Assignee: National Semiconductor CorporationInventors: Joseph E. Herbst, Ian E. Davis
-
Patent number: 5781766Abstract: A programmable compensating device for optimizing performance in a DRAM controller chipset, comprising process monitors for measuring process speeds of integrated circuits in the chipset, evaluation means for comparing the measured process speeds and identifying a slowest integrated circuit, and delay modules for reducing measured process speeds as necessary to match the process speed of the slowest integrated circuit, whereby DRAM access time is minimized to permit more frequent DRAM accesses, thereby optimizing chipset performance.Type: GrantFiled: May 13, 1996Date of Patent: July 14, 1998Assignee: National Semiconductor CorporationInventor: Ian E. Davis
-
Patent number: 5708791Abstract: A system and method cause the computer to automatically detect whether the computer implements a DRAM, and, if so, the architecture of the DRAM. More particularly, the system and method determine the requisite READ protocol for implementing the DRAM, and thus determine whether the DRAM implements a fast page (FP) architecture, an extended data out (EDO) architecture, or a burst extended data out (BEDO) architecture, since each architecture implements a unique READ protocol. From the analysis, the system and method determine if the DRAM is faulty, nonexistent, or of an unknown type. If the DRAM is faulty or of an unknown type, the system and method disable the DRAM.Type: GrantFiled: February 2, 1996Date of Patent: January 13, 1998Assignee: National Semiconductor CorporationInventor: Ian E. Davis
-
Patent number: 5668982Abstract: A computer timing control apparatus including, and a method of using, a controller for providing a toggle-rising signal and a toggle-falling signal, and a half-clock module for sampling the toggle-rising signal and the toggle-falling signal, and generating a module output signal which toggles on the rising edge of the system clock signal if the toggle-rising signal is asserted when sampled, and toggles on the next falling edge of the system clock signal if the toggle-falling signal is asserted when sampled.Type: GrantFiled: November 30, 1995Date of Patent: September 16, 1997Assignee: National Semiconductor CorporationInventor: Ian E. Davis