Abstract: A system for memory word error correction that enables correction of burst errors in memory words. The system is based on an adaptation of two-error correction BCH code which yields burst error correction without increasing the number of error correction bits in the memory words over prior two-error BCH code error correction schemes. The adaptation of two-error correction BCH code when combined with additional techniques for detecting columns of burst errors enables the correction of burst errors and additional random bit errors in memory words.

Abstract: A method and apparatus are shown for performing efficient arithmetic on binary vectors in a finite field. Typically, there is an efficient algorithm within an execution context, such as hardware or software, for performing a selected arithmetic operation on an operand. When the operand is in a first representative format and the efficient algorithm operates in an alternative representation format, then the operand is permutated from the first representative format to the alternative representation format. The efficient algorithm is then performed on the operand in the alternative representation format in order to obtain a result in the alternative representation format. The result is then permutated from the alternative representation format to the first representation format.

Abstract: A method and apparatus are shown for performing efficient arithmetic on binary vectors in a finite field. Typically, there is an efficient algorithm within an execution context, such as hardware or software, for performing a selected arithmetic operation on an operand. When the operand is in a first representative format and the efficient algorithm operates in an alternative representation format, then the operand is permutated from the first representative format to the alternative representation format. The efficient algorithm is then performed on the operand in the alternative representation format in order to obtain a result in the alternative representation format. The result is then permutated from the alternative representation format to the first representation format.

Abstract: A method and apparatus are shown for performing efficient arithmetic on binary vectors in a finite field. Typically, there is an efficient algorithm within an execution context, such as hardware or software, for performing a selected arithmetic operation on an operand. When the operand is in a first representative format and the efficient algorithm operates in an alternative representation format, then the operand is permutated from the first representative format to the alternative representation format. The efficient algorithm is then performed on the operand in the alternative representation format in order to obtain a result in the alternative representation format. The result is then permutated from the alternative representation format to the first representation format.

Abstract: An apparatus and method are shown for multiplying vectors of length n in a finite field. A first vector is circularly shifted in a first shift register under control of a shift signal. A second vector is circularly shifted in a second shift register also under control of the shift signal. An accumulated result vector is circularly shifted in a third shift register under control of the shift signal. Elements of the second vector are logically combined according to a tensor of the multiplication operation to obtain an intermediate result which is combined with the elements of the accumulated result vector to obtain a combination result vector. However, the combination result vector is only loaded into the third shift register when a logic ‘1’ value is present in a first position of the first shift register.