Abstract: There is disclosed current-mode time-interleaved sampling circuitry configured to be driven by substantially sinusoidal clock signals. Such circuitry may be incorporated in ADC circuitry, for example as integrated circuitry on an IC chip. The disclosed circuitry is capable of calibrating itself without being taken off-line.

Abstract: In receiving apparatus of a digital communication system, a received signal burst is demodulated to produce inphase (I) and quadrature (Q) baseband signals which are digitized to provide a set of signal-value pairs for the burst. Each pair consists of an I-value and a corresponding Q-value. The modulation is such that the pairs, if plotted on a complex signal space (I-Q) diagram, would lie substantially on a common circle. To cancel DC offsets in the I and Q signal paths, the average I-value and average Q-value over the burst are found and subtracted respectively from the I- and Q-values of each signal-value pair, to shift the circle so the origin of the I-Q diagram lies within the circle. Then, to restore the DC content of the I and Q signals, the distances I.sub.i1, Q.sub.i2, I.sub.i3 and Q.sub.i4 of signal-value pairs from the I- or Q-axis are averaged in four regions of the I-Q diagram.

Abstract: A voltage storage circuit, for use for example in an analogue-to-digital converter, includes an input switch element connected between an input node (IN) of the circuit and a first plate of a storage capacitor. The other plate of the capacitor is connected to a common terminal 3 of the circuit. A high-impedance amplifier element is connected to the first plate for providing at an output node (OUT) of the circuit an output voltage (V.sub.o) dependent upon the first plate potential (V.sub.c). The amplifier element has an FET input device whose gate electrode is connected to the first plate and whose source and drain electrode potentials are fixed in relation to the first plate potential (V.sub.c). Such a voltage storage circuit avoids charge injection to/from the amplifier element, with consequential charging/discharging of the storage capacitor, which would otherwise result from operation of the amplifier element.

Abstract: A high-speed digital to analogue convertor includes a matrix of cells each including a current source, in which there are provided local decode circuitry within each cell to bring into operation simultaneously all those current sources required to decode any one value.

Abstract: A delta sigma modulator arrangement in which non-ideal characteristics such as noise or offsets in amplifiers or other circuits of the circuits of the arrangement are compensated by chopper stabilisation.

Abstract: An echo canceller (1) for full duplex digital data transmission in a transmitter/receiver unit when connected via a hybrid circuit (2) to one end of a two wire line (3). In order to provide adequate cancellation at a line data rate of 160 kbit/s over 7-8 km, a data bit history of at least 9 bits is used to address a memory having at least 3 partitions (41-44) with the first partition (41) being addressed by a sequence of at least 3 data bits. This partitioning achieves a small memory size, less than 2 kbits, and a small total chip area for integrated circuit realization of the canceller together with a clocking speed for moderate power consumption is maintained by using serial arithmetic (61-63) for adding the partition outputs together with pipelining (D1, D21-D24). An exponentially quantitizing analog-to-digital converter error signal circuit (9), shown in detail in FIG. 2, is used which has wider application to echo cancellers other than the partitioned memory compensation type.

Abstract: A high current drive integrated circuit amplifier in which the quiescent currents in the output transistors are controlled by control current signals which are applied to respective input signal amplifiers and which are of values determined by currents flowing in respective current sensing transistors associated with the output transistors. The control arrangement ensures that the output transistors can not be driven to a non-conducting condition.

Abstract: A voltage storage circuit, for use for example in an analogue-to-digital converter, includes an input switch element connected between an input node (IN) of the circuit and a first plate of a storage capacitor. The other plate of the capacitor is connected to a common terminal 3 of the circuit. A high-impedance amplifier element is connected to the first plate for providing at an output node (OUT) of the circuit an output voltage (V.sub.o) dependent upon the first plate potential (V.sub.c). The amplifier element has an FET input device whose gate electrode is connected to the first plate and whose source and drain electrode potentials are fixed in relation to the first plate potential (V.sub.c).