Abstract: According to a first general aspect of the present invention, there is provided a logic arrangement for reducing incidence of errors in connections between a power consumer apparatus and a power supply apparatus, the logic arrangement comprising: a pattern-generating component for generating an identifiable pattern in a load to be drawn from a power supply connection to a power supply apparatus; and a testing component for monitoring across a signal connection to the power supply apparatus, the testing component monitoring for a change in the load corresponding to the pattern. A positive result of the testing by the testing component indicates a correct configuration. Additional embodiments are also presented.

Abstract: A method and apparatus for recovery from faults in a loop network (500) is provided. The loop network (500) has a plurality of ports (520, 530, 532, 534) serially connected with means for bypassing the ports (520, 530, 532, 534) from the loop network (500). A control device (522, 524) is provided with bypass control over at least one of the ports (530, 532, 534). A host means (502) sends a command to the control device (522, 524) at regular intervals and the control device (522, 524) has a counter which restarts a time period at the receipt of each command. If the time period expires, the control device (522, 524) activates the means for bypassing all the ports (530, 532, 534) under its control. The loop network (500) may have two loops (516, 518) with at least some of the ports (520, 530, 532, 534) common to both loops (516, 518).

Abstract: An apparatus for a node of a peer-to-peer network having a plurality of nodes comprises one or more I/O adapters; a cache component; one or more inter-node routing components; a memory mapping component for presenting to the I/O adapters a single address space mapped across a plurality of memory elements each associated with the cache component; and a direct memory access component for performing a memory operation on the memory elements via the memory mapping component on behalf of the I/O adapters.

Abstract: A copy engine (104) is provided as an interface between firmware (108) and memory space (106) for carrying out copy operations. The copy engine has a first register (202, 203) to point to a first address and a second register (204, 205) to point to a second address. One of the first and second addresses is a source address and one is a destination address for data to be copied. The copy engine (104) also has a control register (201). The control register (201) includes a count of the amount of memory space required by a copy operation, an indication of the direction of the copy operation from the first address to the second address or from the second address to the first address, and an indication of whether the first memory address is incremented or decremented. The copy engine (104) includes a locking mechanism for locking the copy engine (104) during a copy operation. The copy engine (104) also includes a serialisation mechanism in which a write is made to the control register (201) of zero count.

Abstract: A system for detecting write errors in a storage device is disclosed. The system comprises a storage device; within the storage device, means for storing one or more data blocks in a storage group, the storage group comprising the one or more data blocks and a check block, wherein the check block comprises one of the group of: a combination of the one or more data blocks of the storage group, a combination of one or more bits of a logical block address associated with the storage group, and a combination of one or more bits of a phase field that is updated each time the storage group is written; means for updating the check block each time the storage group is written; and means for detecting write errors by checking the check block.