Patents by Inventor Ian R. Bratt

Ian R. Bratt has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Caching in multicore and multiprocessor architectures
    Patent number: 8560780
    Abstract: A multicore processor comprises a plurality of cache memories, and a plurality of processor cores, each associated with one of the cache memories. Each of at least some of the cache memories is configured to maintain at least a portion of the cache memory in which each cache line is dynamically managed as either local to the associated processor core or shared among multiple processor cores.
    Type: Grant
    Filed: July 20, 2012
    Date of Patent: October 15, 2013
    Assignee: Tilera Corporation
    Inventors: Anant Agarwal, Ian R. Bratt, Matthew Mattina
  • Caching in multicore and multiprocessor architectures
    Patent number: 8234451
    Abstract: A multicore processor comprises a plurality of cache memories, and a plurality of processor cores, each associated with one of the cache memories. Each of at least some of the cache memories is configured to maintain at least a portion of the cache memory in which each cache line is dynamically managed as either local to the associated processor core or shared among multiple processor cores.
    Type: Grant
    Filed: July 25, 2011
    Date of Patent: July 31, 2012
    Assignee: Tilera Corporation
    Inventors: Anant Agarwal, Ian R. Bratt, Matthew Mattina
  • Caching in multicore and multiprocessor architectures
    Patent number: 8112581
    Abstract: A multicore processor comprises a plurality of cache memories; a plurality of processor cores, each associated with one of the cache memories; one or more memory interfaces providing memory access paths from the cache memories to a main memory; and one or more directory controllers for respective portions of the main memory, each associated with corresponding storage for directory state. Each corresponding storage provides space for maintaining directory state for each memory line that is indicated as stored in at least one of the cache memories such that the space for maintaining directory state is independent of the size of the main memory.
    Type: Grant
    Filed: December 2, 2010
    Date of Patent: February 7, 2012
    Assignee: Tilera Corporation
    Inventors: Anant Agarwal, Ian R. Bratt, Matthew Mattina
  • Caching in multicore and multiprocessor architectures
    Patent number: 7987321
    Abstract: A multicore processor comprises a plurality of cache memories, and a plurality of processor cores, each associated with one of the cache memories. Each of at least some of the cache memories is configured to maintain at least a portion of the cache memory in which each cache line is dynamically managed as either local to the associated processor core or shared among multiple processor cores.
    Type: Grant
    Filed: December 13, 2010
    Date of Patent: July 26, 2011
    Assignee: Tilera Corporation
    Inventors: Anant Agarwal, Ian R. Bratt, Matthew Mattina
  • Caching in multicore and multiprocessor architectures
    Patent number: 7853755
    Abstract: A multicore processor comprises a plurality of cache memories, and a plurality of processor cores, each associated with one of the cache memories. Each of at least some of the cache memories is configured to maintain at least a portion of the cache memory in which each cache line is dynamically managed as either local to the associated processor core or shared among multiple processor cores.
    Type: Grant
    Filed: May 25, 2007
    Date of Patent: December 14, 2010
    Assignee: Tilera Corporation
    Inventors: Anant Agarwal, Ian R. Bratt, Matthew Mattina
  • Caching in multicore and multiprocessor architectures
    Patent number: 7853754
    Abstract: A multicore processor comprises a plurality of cache memories; a plurality of processor cores, each associated with one of the cache memories; one or more memory interfaces providing memory access paths from the cache memories to a main memory; and one or more directory controllers for respective portions of the main memory, each associated with corresponding storage for directory state. Each corresponding storage provides space for maintaining directory state for each memory line that is indicated as stored in at least one of the cache memories such that the space for maintaining directory state is independent of the size of the main memory.
    Type: Grant
    Filed: May 25, 2007
    Date of Patent: December 14, 2010
    Assignee: Tilera Corporation
    Inventors: Anant Agarwal, Ian R. Bratt, Matthew Mattina
  • Caching in multicore and multiprocessor architectures
    Patent number: 7805575
    Abstract: A multicore processor comprises a plurality of cache memories; a plurality of processor cores, each associated with one of the cache memories; and a plurality of memory interfaces providing memory access paths from the cache memories to a main memory, at least some of the memory interfaces providing access paths to the main memory for multiple of the cache memories. Each of the memory interfaces is associated with a corresponding portion of the main memory, and includes a directory controller for the portion of the main memory.
    Type: Grant
    Filed: May 25, 2007
    Date of Patent: September 28, 2010
    Assignee: Tilera Corporation
    Inventors: Anant Agarwal, Ian R. Bratt, Matthew Mattina
  • Caching in multicore and multiprocessor architectures
    Patent number: 7774553
    Abstract: A multicore processor comprises a plurality of cache memories; a plurality of processor cores, each associated with one of the cache memories; and a plurality of memory interfaces providing memory access paths from the cache memories to a main memory, at least some of the memory interfaces providing access paths to the main memory for multiple of the cache memories. Each of the memory interfaces is associated with a corresponding portion of the main memory, and includes a directory controller for the portion of the main memory.
    Type: Grant
    Filed: May 25, 2007
    Date of Patent: August 10, 2010
    Assignee: Tilera Corporation
    Inventors: Anant Agarwal, Ian R. Bratt, Matthew Mattina