Abstract: Embodiments of the present disclosure describe multi-threshold voltage devices and associated techniques and configurations. In one embodiment, an apparatus includes a semiconductor substrate, a channel body disposed on the semiconductor substrate, a first gate electrode having a first thickness coupled with the channel body and a second gate electrode having a second thickness coupled with the channel body, wherein the first thickness is greater than the second thickness. Other embodiments may be described and/or claimed.

Abstract: Embodiments of the present disclosure describe multi-threshold voltage devices and associated techniques and configurations. In one embodiment, an apparatus includes a semiconductor substrate, a channel body disposed on the semiconductor substrate, a first gate electrode having a first thickness coupled with the channel body and a second gate electrode having a second thickness coupled with the channel body, wherein the first thickness is greater than the second thickness. Other embodiments may be described and/or claimed.

Abstract: Embodiments of the present disclosure describe multi-threshold voltage devices and associated techniques and configurations. In one embodiment, an apparatus includes a semiconductor substrate, a channel body disposed on the semiconductor substrate, a first gate electrode having a first thickness coupled with the channel body and a second gate electrode having a second thickness coupled with the channel body, wherein the first thickness is greater than the second thickness. Other embodiments may be described and/or claimed.

Abstract: Embodiments of the present disclosure describe multi-threshold voltage devices and associated techniques and configurations. In one embodiment, an apparatus includes a semiconductor substrate, a channel body disposed on the semiconductor substrate, a first gate electrode having a first thickness coupled with the channel body and a second gate electrode having a second thickness coupled with the channel body, wherein the first thickness is greater than the second thickness. Other embodiments may be described and/or claimed.

Abstract: Embodiments of the present disclosure describe multi-threshold voltage devices and associated techniques and configurations. In one embodiment, an apparatus includes a semiconductor substrate, a channel body disposed on the semiconductor substrate, a first gate electrode having a first thickness coupled with the channel body and a second gate electrode having a second thickness coupled with the channel body, wherein the first thickness is greater than the second thickness. Other embodiments may be described and/or claimed.

Abstract: Embodiments of the present disclosure describe multi-threshold voltage devices and associated techniques and configurations. In one embodiment, an apparatus includes a semiconductor substrate, a channel body disposed on the semiconductor substrate, a first gate electrode having a first thickness coupled with the channel body and a second gate electrode having a second thickness coupled with the channel body, wherein the first thickness is greater than the second thickness. Other embodiments may be described and/or claimed.

Abstract: Embodiments of the present disclosure describe multi-threshold voltage devices and associated techniques and configurations. In one embodiment, an apparatus includes a semiconductor substrate, a channel body disposed on the semiconductor substrate, a first gate electrode having a first thickness coupled with the channel body and a second gate electrode having a second thickness coupled with the channel body, wherein the first thickness is greater than the second thickness. Other embodiments may be described and/or claimed.

Abstract: Embodiments of the present disclosure describe multi-threshold voltage devices and associated techniques and configurations. In one embodiment, an apparatus includes a semiconductor substrate, a channel body disposed on the semiconductor substrate, a first gate electrode having a first thickness coupled with the channel body and a second gate electrode having a second thickness coupled with the channel body, wherein the first thickness is greater than the second thickness. Other embodiments may be described and/or claimed.

Abstract: Embodiments of the present disclosure describe multi-threshold voltage devices and associated techniques and configurations. In one embodiment, an apparatus includes a semiconductor substrate, a channel body disposed on the semiconductor substrate, a first gate electrode having a first thickness coupled with the channel body and a second gate electrode having a second thickness coupled with the channel body, wherein the first thickness is greater than the second thickness. Other embodiments may be described and/or claimed.

Abstract: The present invention teaches a method for fabricating a bipolar junction transistor ("BJT") from a semiconductor substrate having a base region, wherein the BJT comprises an increased Early voltage. The method initially comprises the step of forming a patterned interlevel dielectric layer superjacent the substrate such that a segment of the substrate is exposed. Subsequently, a contact comprising a material having a grain size smaller than polycrystalline silicon is formed superjacent the patterned interlevel dielectric layer and the segment of the substrate exposed. The contact is then implanted with a dopant. Once implanted, the substrate is annealed to enable the dopant to diffuse from the contact into the base region impeded by the grain size to form an emitter region and thereby increase the Early voltage of the bipolar junction transistor.

Abstract: The present invention teaches a method and structure of enhancing the current gain characteristics of a bipolar junction transistor using a semiconductor substrate comprising a base, an emitter and a collector and an interface at the emitter, such that a carrier current conducts between the base and the emitter. Further, a first polysilicon layer is formed superjacent the interface, and is implanted with O.sub.2. Subsequently, the substrate is heated such that the emitter interface is obstructed by a silicon dioxide formation, thereby blocking a portion of carrier current from passing through the interface.

Abstract: The present invention teaches a method of making an isolation trench. First, a silicon on insulator ("SOI") structure is provided having a conductive layer superjacent the insulator of the SOI. Second, a trench is formed down to the insulator of the SOI, thereby creating a first and second conductive region. Third, a first silicon dioxide layer is formed conformally with the sidewalls of the first and second conductive region. Fourth, a second silicon dioxide layer is formed conformally and superjacent the first silicon dioxide layer. Fifth, the remaining areas unfilled in the trench are filled with an undoped polysilicon filling. Sixth, the polysilicon layer is planarized. Seventh, an oxide cap is formed on top of the polysilicon refill. Eight, an isolation mask is formed, and the active area openings within the structure are etched down to the single crystal silicon.

Abstract: The present invention teaches a method and structure of enhancing the current gain characteristics of a bipolar junction transistor. The method comprises the step of forming a patterned silicon dioxide layer superjacent a semiconductor substrate comprising a base, an emitter and a collector, such that a carrier current conducts between the base and the emitter. The silicon dioxide layer forms an interface on the substrate at the emitter. Further, a first polysilicon layer is formed superjacent both the patterned silicon dioxide layer and the interface, and is implanted with O.sub.2. Subsequently, the substrate is heated such that the emitter interface is obstructed by a silicon dioxide formation, thereby blocking a portion of carrier current from passing through the interface.