Patents by Inventor Ibrahim M. Elfadel
Ibrahim M. Elfadel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8036728Abstract: The present disclosure describes a method and an apparatus for analyzing measured signals using various processing techniques. In certain embodiments, the measured signals are physiological signals. In certain embodiments, the measurements relate to blood constituent measurements including blood oxygen saturation.Type: GrantFiled: June 21, 2007Date of Patent: October 11, 2011Assignee: MASIMO CorporationInventors: Mohamed K. Diab, Esmaiel Kiani-Azarbayjany, Ibrahim M. Elfadel, Rex J. McCarthy, Walter M. Weber, Robert A. Smith
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Publication number: 20110228600Abstract: Systems, methods, and devices for iteratively writing contents to memory locations are provided. A statistical model is used to determine a sequence of pulses to write desired contents to a memory location. The contents can be expressed as a resistance value in a range to store one or more bits in a memory cell. For phase change memory, an adaptive reset pulse and one or more annealing pulses are selected based on a desired resistance range. Reading the resistance value of the memory cell can provide feedback to determine adjustments in an overall pulse application strategy. The statistical model and a look up table can be used to select and modify pulses. Adaptively updating the statistical model and look up table may reduce the number of looping iterations to shift the resistance value of the memory cell into the desired resistance range.Type: ApplicationFiled: June 1, 2011Publication date: September 22, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Matthew J. Breitwisch, Roger W. Cheek, Stefanie R. Chiras, Ibrahim M. Elfadel, Michele M. Franceschini, John P. Karidis, Luis A. Lastras-Montano, Thomas Mittelholzer, Mayank Sharma
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Patent number: 8023345Abstract: Systems, methods, and devices for iteratively writing contents to memory locations are provided. A statistical model is used to determine a sequence of pulses to write desired contents to a memory location. The contents can be expressed as a resistance value in a range to store one or more bits in a memory cell. For phase change memory, an adaptive reset pulse and one or more annealing pulses are selected based on a desired resistance range. Reading the resistance value of the memory cell can provide feedback to determine adjustments in an overall pulse application strategy. The statistical model and a look up table can be used to select and modify pulses. Adaptively updating the statistical model and look up table may reduce the number of looping iterations to shift the resistance value of the memory cell into the desired resistance range.Type: GrantFiled: February 24, 2009Date of Patent: September 20, 2011Assignee: International Business Machines CorporationInventors: Matthew J. Breitwisch, Roger W. Cheek, Stefanie R. Chiras, Ibrahim M. Elfadel, Michele M. Franceschini, John P. Karidis, Luis A. Lastras-Montano, Thomas Mittelholzer, Mayank Sharma
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Patent number: 8019400Abstract: The present disclosure describes a method and an apparatus for analyzing measured signals using various processing techniques. In certain embodiments, the measured signals are physiological signals. In certain embodiments, the measurements relate to blood constituent measurements including blood oxygen saturation.Type: GrantFiled: August 20, 2007Date of Patent: September 13, 2011Assignee: MASIMO CorporationInventors: Mohamed K. Diab, Esmaiel Kiani-Azarbayjany, Ibrahim M. Elfadel, Rex J. McCarthy, Walter M. Weber, Robert A. Smith
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Patent number: 7979825Abstract: A method and system for determining electrical parameter data for a layer of an integrated circuit that can include a nominal electrical parameter value, and sensitivity values which represent the sensitivities of the nominal electrical parameter value to variations in the nominal parameter values. A template of the layer geometry is provided from a portion of which a set of linear equations are developed and which equations are solved using a two step method and from which solution the nominal electrical parameter values are determined. An auxiliary set of the original linear equations is developed from the original set using the adjoint method and from the solution of the auxiliary set using the two step method the sensitivity values are calculated.Type: GrantFiled: March 31, 2008Date of Patent: July 12, 2011Assignee: International Business Machines CorporationInventors: Ibrahim M. Elfadel, Tarek A. El Moselhy
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Patent number: 7979246Abstract: Transmission line macromodels can be classified into main categories of delay-extraction and rational approximation. The exponential solution of the Telegrapher's Equation is used to create a system and method that enable a time-domain circuit simulator to automatically select the most appropriate macromodel for a given transmission line structure.Type: GrantFiled: March 31, 2008Date of Patent: July 12, 2011Assignee: International Business Machines CorporationInventor: Ibrahim M. Elfadel
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Publication number: 20110161908Abstract: A computer system selects a signal conductor from an electronic circuit design layout and assigns a first potential to the selected signal conductor. Next, the computer system assigns a second potential to other signal conductors included in the electronic circuit design layout. The computer system then selects a metal fill from the electronic circuit design layout, which is void from carrying an electrical signal, and generates a zero charge equation for the selected metal fill. The zero charge equation establishes that a total charge residing on the selected metal fill is equal to zero. The computer system includes the zero charge equation in a system of equations, which includes grid point potential equations, and solves the system of equations. In turn, the computer system computes capacitance values for the signal conductors based upon the system of equation solutions, and simulates the electronic circuit design layout using the computed capacitance values.Type: ApplicationFiled: December 29, 2009Publication date: June 30, 2011Applicant: International Business Machines CorporationInventors: IBRAHIM M. ELFADEL, Tarek Ali El Moselhy, David J. Widiger
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Patent number: 7921004Abstract: Methods and apparatus are provided for analyzing transmission lines with decoupling of connectors and other circuit elements. According to one aspect of the invention, circuits with one or more parasitic elements are analyzed by partitioning at least one of the parasitic elements in a transverse manner; identifying a plurality of subcircuits each comprised of partitioned circuit elements from the plurality of transmission lines and one or more parasitic elements in a given path; wherein each of the subcircuits is associated with a path in the circuit; performing a waveform relaxation analysis between each of the subcircuits; and repeating the step of performing the waveform relaxation analysis using waveforms determined in a previous iteration until convergence to a resultant waveform has occurred. The circuit can optionally further comprise one or more transmission lines which would also be partitioned in a transverse manner.Type: GrantFiled: April 2, 2008Date of Patent: April 5, 2011Assignee: International Business Machines CorporationInventors: Ibrahim M. Elfadel, Hao Ming Huang, Albert E. Ruehli
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Publication number: 20110078642Abstract: Computing the gradients of capacitances in an integrated circuit chip layout with respect to design and process parameters is described. Included is a shape processing engine in the form of a variational mapping engine and a capacitance calculation engine that includes a gradient calculation engine. The variational mapping engine translates physical parameter variations into variations on the edges of the elementary patterns to which the layout of the integrated circuit is decomposed. The gradient calculation engine computes capacitance gradients by combining information from two sources. The first source consists of pre-existing gradients in a capacitance lookup table. The second source consists of analytical expressions of capacitance correction factors.Type: ApplicationFiled: September 30, 2009Publication date: March 31, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ibrahim M. Elfadel, Lewis William Dewey, III, Tarek A. El-Moselhy, David J. Widiger, Patrick M. Williams
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Publication number: 20110069521Abstract: An analog memory having adjustable write bins including a system for writing to the memory. The system includes a write apparatus interpreting one or more write control signals, generating a write signal, and applying the write signal at a selected memory location to store a desired content. The selected memory location is subject to data dependent noise and is capable of storing a range of values grouped into ānā bins configured such that the average cost to write to at least ān-1ā of the bins is within a threshold of a target cost for the selected analog memory location. The system also includes a read apparatus. The system further includes write control circuitry that includes a write signal selector selecting the one or more write control signals responsive to the desired content, current content of the selected memory location, and a bin associated with the desired content.Type: ApplicationFiled: September 24, 2009Publication date: March 24, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ibrahim M. Elfadel, Michele M. Franceschini, Luis A. Lastras-Montano, Thomas Mittelholzer, Mayank Sharma
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Patent number: 7913202Abstract: A design structure for a 3D chip having at least one I/O layer connected to other 3D chip layers by a vertical bus such that the I/O layer(s) may accommodate protection and off-chip device drive circuits, customization circuits, translation circuits, conversions circuits and/or built-in self-test circuits capable of comprehensive chip or wafer level testing wherein the I/O layers function as a testhead. Substitution of I/O circuits or structures may be performed using E-fuses or the like responsive to such testing.Type: GrantFiled: November 27, 2007Date of Patent: March 22, 2011Assignee: International Business Machines CorporationInventors: Kerry Bernstein, Paul Coteus, Ibrahim M. Elfadel, Philip Emma, Daniel Friedman, Ruchir Puri, Mark B. Ritter, Jeannine Trewhella, Albert M. Young
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Publication number: 20100277989Abstract: Providing increased capacity in heterogeneous storage elements including a method for storing data including a write process writing to a memory and a read process reading from the memory. Physical characteristics of memory cells in the memory support different sets of data levels. The write process takes into account the different sets of data levels when writing to the memory. The read process first obtains data in the memory and subsequently determines how to interpret the data.Type: ApplicationFiled: April 30, 2009Publication date: November 4, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ibrahim M. Elfadel, Michele Franceschini, Ashish Jagmohan, Luis A. Lastras-Montano, Mayank Sharma
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Patent number: 7827019Abstract: A passive macromodel for lossy, dispersive multiconductor transmission lines uses a multiplicative approximation of the matrix exponential known as the Lie product. The circuit implementation of the macromodel is a cascade of elementary cells, each cell being the combination of a pure delay element and a lumped circuit representing the transmission line losses. Compared with passive rational macromodeling, the Lie product macromodel is capable of efficiently simulating long, low-loss multiconductor transmission lines while preserving passivity. This result is combined with transmission line theory to derive a time-domain error criterion for the Lie product macromodel. This criterion is used to determine the minimum number of cells needed in the macromodel to assure that the magnitude of the time-domain error is less than a given engineering tolerance.Type: GrantFiled: May 22, 2008Date of Patent: November 2, 2010Assignee: International Business Machines CorporationInventors: Ibrahim M. Elfadel, Hao Ming Huang
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Publication number: 20100262940Abstract: The Width Bias Calculator (WBC) calculates electrical values by effectively averaging the electrical values to either side of a target wire shape whereby values are approximated for design validation without a significant impact on performance or memory consumption.Type: ApplicationFiled: April 14, 2009Publication date: October 14, 2010Applicant: International Business Machines CorporationInventors: Lewis William Dewey, III, Ibrahim M. Elfadel, David J. Widiger
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Publication number: 20100214829Abstract: Systems, methods, and devices for iteratively writing contents to memory locations are provided. A statistical model is used to determine a sequence of pulses to write desired contents to a memory location. The contents can be expressed as a resistance value in a range to store one or more bits in a memory cell. For phase change memory, an adaptive reset pulse and one or more annealing pulses are selected based on a desired resistance range. Reading the resistance value of the memory cell can provide feedback to determine adjustments in an overall pulse application strategy. The statistical model and a look up table can be used to select and modify pulses. Adaptively updating the statistical model and look up table may reduce the number of looping iterations to shift the resistance value of the memory cell into the desired resistance range.Type: ApplicationFiled: February 24, 2009Publication date: August 26, 2010Applicant: International Business Machines CorporationInventors: Matthew J. Breitwisch, Roger W. Cheek, Stefanie R. Chiras, Ibrahim M. Elfadel, Michele M. Franceschini, John P. Karidis, Luis A. Lastras-Montano, Thomas Mittelholzer, Mayank Sharma
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Patent number: 7723207Abstract: A three dimensional (3D) integrated circuit (IC), 3D IC chip and method of fabricating a 3D IC chip. The chip includes multiple layers of circuits, e.g., silicon insulator (SOI) CMOS IC layers, each including circuit elements. The layers may be formed in parallel and one layer attached to another to form a laminated 3D chip.Type: GrantFiled: April 19, 2007Date of Patent: May 25, 2010Assignee: International Business Machines CorporationInventors: Syed M. Alam, Ibrahim M. Elfadel, Kathryn W Guarini, Meikei Ieong, Prabhakar N. Kudva, David S. Kung, Mark A. Lavin, Arifur Rahman
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Publication number: 20100122222Abstract: Capacitance extraction techniques are provided. In one aspect, a method for analyzing variational coupling capacitance between conductors in an integrated circuit design is provided. The method comprises the following steps. Coupling capacitance is computed between conductors of interest from the design using a set of floating random walk paths. One or more of the conductors are perturbed. Any of the floating random walk paths affected by the perturbation are modified. The coupling capacitance between the conductors of interest is recomputed to include the modified floating random walk paths.Type: ApplicationFiled: November 9, 2008Publication date: May 13, 2010Applicant: International Business Machines CorporationInventors: Ibrahim M. Elfadel, Tarek A. El-Moselhy
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Publication number: 20100122223Abstract: Techniques for capacitance extraction from an integrated circuit design are provided. In one aspect, a method for determining coupling capacitance between conductors within an integrated circuit design is provided comprising the following steps. A three-dimensional representation of the integrated circuit design is generated based on three-dimensional technology and three-dimensional geometric input about the integrated circuit. Conductors of interest are selected from the design. Three-dimensional coupling capacitance between the selected conductors is determined. Further, a first and a second conductor can be selected from the conductors of interest. A Gaussian surface can be created around the first conductor. A random walk path can be created starting at a randomly selected point on the Gaussian surface and terminating on the second conductor.Type: ApplicationFiled: November 9, 2008Publication date: May 13, 2010Applicant: International Business Machines CorporationInventors: Ibrahim M. Elfadel, Tarek A. El-Moselhy
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Publication number: 20090248335Abstract: A method and system for determining electrical parameter data for a layer of an integrated circuit that can include a nominal electrical parameter value, and sensitivity values which represent the sensitivities of the nominal electrical parameter value to variations in the nominal parameter values. A template of the layer geometry is provided from a portion of which a set of linear equations are developed and which equations are solved using a two step method and from which solution the nominal electrical parameter values are determined. An auxiliary set of the original linear equations is developed from the original set using the adjoint method and from the solution of the auxiliary set using the two step method the sensitivity values are calculated.Type: ApplicationFiled: March 31, 2008Publication date: October 1, 2009Inventors: Ibrahim M. Elfadel, Tarek A. El Moselhy
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Publication number: 20090182211Abstract: The present disclosure describes a method and an apparatus for analyzing measured signals using various processing techniques. In certain embodiments, the measured signals are physiological signals. In certain embodiments, the measurements relate to blood constituent measurements including blood oxygen saturation.Type: ApplicationFiled: March 24, 2009Publication date: July 16, 2009Applicant: MASIMO CORPORATIONInventors: Mohamed K. Diab, Esmaiel Kiani-Azarbayjany, Ibrahim M. Elfadel, Rex J. McCarthy, Walter M. Weber, Robert A. Smith