Abstract: A semiconductor device in which a semiconductor chip 1 is bonded by a metal bond 2 to one surface of a heat sink 4 formed of a material with a thermal expansion coefficient is close to he semiconductor chip 1, the heat sink 4 is glued to a stiffener with a silicon adhesive 5 with an elastic modulus of 10 MPa or less, a TAB tape 9 is glued to the stiffener 3 with an epoxy adhesive 6, and the semiconductor chip 1 is sealed with an epoxy sealing resin 8 with an elastic modulus of 10 GPa or more for protection from outside.

Abstract: In a multi-chip module, a plurality of semiconductor chips are mounted on a single wiring board. Upper surfaces of the chips are covered with a single heat spread plate, and the whole space around the chips sandwiched between the wiring board and the heat spread plate is filled with resin. The semiconductor chips are interconnected through the resin so that any stress exerted on any chips is dispersed. This diminishes the occurrence of cracks caused by stress concentration. Since the chips and the heat spread plate are bonded together with resin, even if there are variations in size of the chips, both can be bonded easily. Further, the bonding of all the chips and the heat spread plate can be done in a single process.

Abstract: As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the “Lead-On-Chip” or “Chip-On-Lead” structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.

Abstract: A semiconductor device including a semiconductor chip having connection terminals in a peripheral part of a main surface thereof; an elastic body disposed on the main surface leaving the connection terminals exposed; an insulating tape formed on the elastic body and having openings in areas where the connection terminals are situated; plural leads formed on the top surface of the insulating tape, one end of each lead being connected to one of the connection terminals and the other end being disposed on the elastic body; plural bump electrodes formed on the other ends of the plural leads; and a resin body for sealing the connection terminals and one end of each of the leads, wherein the insulating tape protrudes beyond the chip where the plural connection terminals are arranged, and wherein the shape of the resin body is restricted by the protruding part of the insulating tape.

Abstract: Disclosed is a technique capable of enhancing the degree of freedom in the layout of a rerouting layer in a wafer level CSP in which defect repairing is performed by cutting a fuse. More specifically, after the defect repairing is performed by irradiating a laser beam to a fuse, an organic passivation layer (photo-sensitive polyimide layer) is filled in a fuse opening. Thereafter, a rerouting layer, a bump land, an uppermost wiring layer, and a solder bump are formed on the organic passivation layer. In the following steps of the defect repairing, the baking process to cure an elastomer layer and the uppermost protection layer is conducted at a temperature below 260° C. in order to prevent the variance of the refresh times of memory cells.

Abstract: A semiconductor device in which a semiconductor chip 1 is bonded by a metal bond 2 to one surface of a heat sink 4 formed of a material with a thermal expansion coefficient is close to he semiconductor chip 1, the heat sink 4 is glued to a stiffener with a silicon adhesive 5 with an elastic modulus of 10 MPa or less, a TAB tape 9 is glued to the stiffener 3 with an epoxy adhesive 6, and the semiconductor chip 1 is sealed with an epoxy sealing resin 8 with an elastic modulus of 10 GPa or more for protection from outside.

Abstract: A semiconductor integrated circuit device includes a semiconductor substrate, a circuit element formed on one major surface of the semiconductor substrate and constituting an integrated circuit having a plurality of functions or a plurality of characteristics, an internal connection terminal, connected to the integrated circuit, for selecting one of the plurality of functions or one of the characteristics in the integrated circuit, an insulating layer covering the internal connection terminal such that the internal connection terminal is selectively exposed, and an external connection terminal arranged on the insulating layer. One of the plurality of functions or one of the plurality of characteristics is selected by a connection state between the internal connection terminal and the external connection terminal.

Abstract: A semiconductor device in which a semiconductor chip 1 is bonded by a metal bond 2 to one surface of a heat sink 4 formed of a material with a thermal expansion coefficient is close to the semiconductor chip 1, the heat sink 4 is glued to a stiffener with a silicon adhesive 5 with an elastic modulus of 10 MPa or less, a TAB tape 9 is glued to the stiffener 3 with an epoxy adhesive 6, and the semiconductor chip 1 is sealed with an epoxy sealing resin 8 with an elastic modulus of 10 GPa or more for protection from outside.

Abstract: A semiconductor device in which a semiconductor chip 1 is bonded by a metal bond 2 to one surface of a heat sink 4 formed of a material with a thermal expansion coefficient is close to he semiconductor chip 1, the heat sink 4 is glued to a stiffener with a silicon adhesive 5 with an elastic modulus of 10 MPa or less, a TAB tape 9 is glued to the stiffener 3 with an epoxy adhesive 6, and the semiconductor chip 1 is sealed with an epoxy sealing resin 8 with an elastic modulus of 10 GPa or more for protection from outside.

Abstract: The object of the present invention is to realize a semiconductor device enabling a flip chip connection without use of underfill.

Abstract: A semiconductor device including a semiconductor chip having connection terminals in a peripheral part of a main surface thereof; an elastic body disposed on the main surface leaving the connection terminals exposed; an insulating tape formed on the elastic body and having openings in areas where the connection terminals are situated; plural leads formed on the top surface of the insulating tape, one end of each lead being connected to one of the connection terminals and the other end being disposed on the elastic body; plural bump electrodes formed on the other ends of the plural leads; and a resin body for sealing the connection terminals and one end of each of the leads, wherein the insulating tape protrudes beyond the chip where the plural connection terminals are arranged, and wherein the shape of the resin body is restricted by the protruding part of the insulating tape.

Abstract: A semiconductor device including a semiconductor chip having connection terminals in a peripheral part of a main surface thereof; an elastic body disposed on the main surface leaving the connection terminals exposed; an insulating tape formed on the elastic body and having openings in areas where the connection terminals are situated; plural leads formed on the top surface of the insulating tape, one end of each lead being connected to one of the connection terminals and the other end being disposed on the elastic body; plural bump electrodes formed on the other ends of the plural leads; and a resin body for sealing the connection terminals and one end of each of the leads, wherein the insulating tape protrudes beyond the chip where the plural connection terminals are arranged, and wherein the shape of the resin body is restricted by the protruding part of the insulating tape.

Abstract: The present invention is a semiconductor device having the semiconductor element 1 obtained by cutting a semiconductor wafer with the electrode pad 2 formed on one side along the scribe line, the semiconductor element protective layer 7 on the semiconductor element 1 which has the opening 7(1) on the pad 2, the stress cushioning layer 3 on the layer 7 which has the opening 3(1) on the pad 2, the lead wire portion 4 reaching the layer 3 from the electrode pad 2 via the openings 7(1) and 3(1), the external electrodes 6 on the lead wire portion 4, and the conductor protective layer 5 on the layer 3 and the layer 7, the layer 3, and the conductor protective layer 5 form the respective end faces on the end surface 1(1) of the semiconductor element 1 inside the scribe line and expose the range from the end face of the end surface 1(1) to the inside of the scribe line.

Abstract: A manufacturing method makes it possible to produce a semiconductor apparatus which is outstanding in mounting reliability at a high manufacturing yield rate. A semiconductor apparatus, in which, on the surface of a semiconductor chip with a circuit and an electrode formed thereon, a stress cushioning layer is provided, except for a part where the electrode is, has a wiring layer connected to the electrode on the stress cushioning layer, an external protection film on the wiring layer and stress cushioning layer, a window where a part of the wiring layer is exposed at a predetermined location of the external protection film, and an external electrode which is electrically connected to the wiring layer via the window. The stress cushioning layer, wiring layer, conductor, external protection film, and external electrode are formed on the inside of the end of the semiconductor chip.

Abstract: As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the “Lead-On-Chip” or “Chip-On-Lead” structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.

Abstract: A semiconductor device including a semiconductor chip having connection terminals in a peripheral part of a main surface thereof; an elastic body disposed on the main surface leaving the connection terminals exposed; an insulating tape formed on the elastic body and having openings in areas where the connection terminals are situated; plural leads formed on the top surface of the insulating tape, one end of each lead being connected to one of the connection terminals and the other end being disposed on the elastic body; plural bump electrodes formed on the other ends of the plural leads; and a resin body for sealing the connection terminals and one end of each of the leads, wherein the insulating tape protrudes beyond the chip where the plural connection terminals are arranged, and wherein the shape of the resin body is restricted by the protruding part of the insulating tape.

Abstract: As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the “Lead-On-Chip” or “Chip-On-Lead” structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.

Abstract: As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the “Lead-On-Chip” or “Chip-On-Lead” structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.

Abstract: As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the “Lead-On-Chip” or “Chip-On-Lead” structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.

Abstract: As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the "Lead-On-Chip" or "Chip-On-Lead" structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.