Abstract: A semiconductor device includes a plurality of memories, a sequencer which outputs configuration information, and a memory reconfiguring circuit which reconfigures the memory area in accordance with the configuration information supplied from the sequencer. Since the memory reconfiguring circuit dynamically changes the allocation of the memories, it is possible to reconfigure the memory configuration and freely change the memory size in accordance with the purpose of use.

Abstract: An operation apparatus includes a sequencer controlling states of a plurality of operation devices and a configuration memory storing therein configuration information as setting information for each state in the operation device. In the operation apparatus, a path which requires a data buffer and another path which requires no such a data buffer are provided for inputting data to the operation device, a data buffer control part is provided for controlling selection from these two paths and operation of the data buffer, and contents of path selection and operation control of the data buffer carried out by the data buffer control part are set according to the configuration information.

Abstract: A reconfigurable processor calculates execution times of configuration for executing pipeline processing from hardware configuration information, and fixes a clock cycle until processing ends. A counter compares the fixed clock cycle with the actual number of elapsed clocks, and, when the number of elapsed clocks equals the clock cycle, it is determined that pipeline processing has ended, and a configuration controller is notified of this.

Abstract: A semiconductor device includes a configuration memory for storing configuration data, an arithmetic unit whose circuit configuration can be reconfigured in accordance with the configuration data, and a fixed value memory for storing fixed value data to be supplied to the arithmetic unit. Since the configuration data and fixed value data to be supplied to the arithmetic unit are stored in the different memories, no data area for storing the fixed value data need be set in the configuration memory. This makes it possible to supply a predetermined fixed value to the arithmetic unit by storing only information for reading out fixed value data from the fixed value memory.

Abstract: A reconfigurable processor in which an application can be switched more freely. A switching condition associating section associates output from a plurality of arithmetic and logic unit modules used as switching conditions for switching the operation of an arithmetic and logic unit group with a plurality of states indicative of switching condition codes. When a switching condition code output section decides that a switching condition comes into existence on the basis of the output from the plurality of arithmetic and logic unit modules set as the switching conditions, the switching condition code output section outputs a switching condition code corresponding to the switching condition which comes into existence. When a sequencer accepts the switching condition code, the sequencer switches the arithmetic and logic unit group to a state corresponding to the switching condition code.

Abstract: A reconfigurable processor that finely controls operation without exerting an influence upon other functions. Register groups are connected to input ports of ALUs via selectors. Data inputted to an ALU is held in a register selected by a selector under the control of a sequencer. For example, it is assumed that a register is selected for executing an application. To switch this application to a next application, a selector switches the register to another register to be used in accordance with instructions from the sequencer after the application terminates. In this case, data inputted while the application was being executed remains in the register, so the next application can be executed immediately without exporting the data after the termination of the application.

Abstract: A processor that includes reconfigurable processing circits for performing predetermined processing, in which a compiler is made capable of determining storage of configuration data in a cache. Configuration data for defining a configuration of the processing circuit contains cache operation information defining an operation of a cache. A cache operation information acquisition section acquires cache operation information from the configuration data when the configuration data is selected. A cache control section controls the operation of the cache storing the configuration data, based on the cache operation information. Since the cache operation information is contained in the configuration data, and the operation of the cache storing the configuration data is controlled based on the cache operation information, the compiler is capable of storing the cache operation information in the configuration data, based on a prediction on operations of a program.