Patents by Inventor Ichiro Kohno

Ichiro Kohno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6907585
    Abstract: A method and device are provided for applying logic BIST at speed for large-scale and high-performance logic circuits without increasing test time, and decreasing test costs as a result. In one example, a logic BIST controller is divided into two portions. A clock signal having a small delay is used to drive a partial circuit that supplies a user circuit with a scan enable signal and a clock signal. A clock signal having a large delay is used to drive a partial circuit that supplies the user circuit with a test pattern and collects a test result.
    Type: Grant
    Filed: April 10, 2003
    Date of Patent: June 14, 2005
    Assignee: Renesas Technology Corporation
    Inventor: Ichiro Kohno
  • Patent number: 6806731
    Abstract: A semiconductor integrated circuit device which shortens the time required for testing a divided logic circuit to reduce test cost and a fault-detecting method therefor. The logic circuit is divided into N logic blocks using N+1 scan paths comprises of scan flip-flops each having selectors for selectively picking up the output signals of storage elements which are fed back to the storage elements. A common scan operation may then be carried out on these logic blocks (Logic 1-to Logic N), and a testing operation may be continuously carried out on the logic blocks. The present invention preferably eliminates the overlaps in conventional scan operations, resulting in a shorter test time.
    Type: Grant
    Filed: May 14, 2002
    Date of Patent: October 19, 2004
    Assignee: Renesas Technology Corp.
    Inventor: Ichiro Kohno
  • Publication number: 20030200495
    Abstract: A method and device are provided for applying logic BIST at speed for large-scale and high-performance logic circuits without increasing test time, and decreasing test costs as a result. In one example, a logic BIST controller is divided into two portions. A clock signal having a small delay is used-to drive a partial circuit that supplies a user circuit with a scan enable signal and a clock signal. A clock signal having a large delay is used to drive a partial circuit that supplies the user circuit with a test pattern and collects a test result.
    Type: Application
    Filed: April 10, 2003
    Publication date: October 23, 2003
    Applicant: Hitachi, Ltd.
    Inventor: Ichiro Kohno
  • Publication number: 20020175699
    Abstract: A semiconductor integrated circuit device which shortens the time required for testing a divided logic circuit to reduce test cost and a fault-detecting method therefor. The logic circuit is divided into N logic blocks using N+1 scan paths comprises of scan flip-flops each having selectors for selectively picking up the output signals of storage elements which are fed back to the storage elements. A common scan operation may then be carried out on these logic blocks (Logic 1-to Logic N), and a testing operation may be continuously carried out on the logic blocks. The present invention preferably eliminates the overlaps in conventional scan operations, resulting in a shorter test time.
    Type: Application
    Filed: May 14, 2002
    Publication date: November 28, 2002
    Applicant: Hitachi, Ltd.
    Inventor: Ichiro Kohno
  • Patent number: 6473966
    Abstract: A printer head substrate having a silicon substrate on which heat generating elements and partitions are formed and an orifice plate which adhered to the partitions is placed on a stage of a helicon-wave dry etching system. Helicon-wave dry etching is performed while cooling the printer head substrate by allowing a coolant gas to be intervened between the substrate and the stage. This allows multiple orifices of a desired and adequate shape to be simultaneously and quickly bored in the orifice plate even if a thin film sheet having adhesive layers adhered to both sides thereof is used as the orifice plate, thereby improving the working efficiency.
    Type: Grant
    Filed: January 27, 2000
    Date of Patent: November 5, 2002
    Assignee: Casio Computer Co., Ltd.
    Inventors: Ichiro Kohno, Junji Shiota, Hideki Kamada, Satoshi Kanemitsu, Yoshihiro Kawamura
  • Patent number: 6368515
    Abstract: In a method of manufacturing an ink-jet printer which uses a thin film sheet having adhesive layers respectively formed on the top and bottom sides, as an orifice plate, orifices are formed in the ink-ejecting side of the thin film sheet after the adhesive layer on that ink-ejecting side has been removed. This prevents the formation of the orifices from being adversely affected by any otherwise residual of the adhesive layer and can thus permit accurate formation of orifices of a desired shape. Even if helicon-wave dry etching which ensure fast etching using high-power energy is used to form orifices, therefore, no adhesive layer is thermally expanded to be a residual so that multiple orifices can be formed simultaneously and quickly.
    Type: Grant
    Filed: January 27, 2000
    Date of Patent: April 9, 2002
    Assignee: Casio Computer Co., Ltd.
    Inventors: Katsuzo Kaminishi, Junji Shiota, Ichiro Kohno, Kazuyoshi Arai
  • Patent number: 5392136
    Abstract: Disclosed is a compact, light-weight facsimile apparatus which is reduced in cost, furnished with a large storage capacity and provided with flexibility in terms of handling by utilizing a magnetic tape recording/playback mechanism as a storage source of image data and providing an image data memory on the magnetic tape. Tape-drive control and format are so designed that a code representing that image data has been stored on the tape, management information, which includes transmission/reception control information and information indicating storage position, and the image data are stored on the tape based on a prearranged storage format.
    Type: Grant
    Filed: July 19, 1993
    Date of Patent: February 21, 1995
    Assignee: Canon Kabushiki Kaisha
    Inventors: Hiroshi Nobuta, Ichiro Kohno
  • Patent number: 5258853
    Abstract: Disclosed is a compact, light-weight facsimile apparatus which is reduced in cost, furnished with a large storage capacity and provided with flexibility in terms of handling by utilizing a magnetic tape recording/playback mechanism as a storage source of image data and providing an image data memory on the magnetic tape. Tape-drive control and format are so designed that a code representing that image data has been stored on the tape, management information, which includes transmission/reception control information and information indicating storage position, and the image data are stored on the tape based on a prearranged storage format.
    Type: Grant
    Filed: March 22, 1991
    Date of Patent: November 2, 1993
    Assignee: Canon Kabushiki Kaisha
    Inventors: Hiroshi Nobuta, Ichiro Kohno