Patents by Inventor Ichiro Omura
Ichiro Omura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20070241337Abstract: In a nitride semiconductor device according to one embodiment of the invention, a p-type gallium nitride (GaN) layer electrically connected to a source electrode and extending and projecting to a drain electrode side with respect to a gate electrode is formed on an undoped or n-type aluminum gallium nitride (AlGaN) layer serving as a barrier layer.Type: ApplicationFiled: June 21, 2007Publication date: October 18, 2007Applicant: Kabushiki Kaisha ToshibaInventors: Wataru Saito, Ichiro Omura
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Patent number: 7276773Abstract: A power semiconductor device includes second semiconductor layers of a first conductivity type and third semiconductor layers of a second conductivity type alternately disposed on a first semiconductor layer of the first conductivity type. The device further includes fourth semiconductor layers of the second conductivity type disposed in contact with upper portions of the third semiconductor layers between the second semiconductor layers, and fifth semiconductor layers of the first conductivity type formed in surfaces of the fourth semiconductor layers. The first semiconductor layer is lower in impurity concentration of the first conductivity type than each second semiconductor layer. The third semiconductor layer includes a fundamental portion and an impurity-amount-larger portion formed locally in a depth direction and higher in impurity amount than the fundamental portion.Type: GrantFiled: April 29, 2005Date of Patent: October 2, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Wataru Saito, Ichiro Omura
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Patent number: 7271477Abstract: A power semiconductor device package according to one aspect of the present invention comprises: a plurality of power semiconductor chips which are arranged in a laminated structure so that the plurality of power semiconductor chips are opposing to each other at the surfaces with the same electrical structures, and which are connected in parallel to one another, and are sealed in a sealing resin as one body.Type: GrantFiled: June 16, 2004Date of Patent: September 18, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Wataru Saito, Ichiro Omura
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Patent number: 7271429Abstract: In a nitride semiconductor device according to one embodiment of the invention, a p-type gallium nitride (GaN) layer electrically connected to a source electrode and extending and projecting to a drain electrode side with respect to a gate electrode is formed on an undoped or n-type aluminum gallium nitride (AlGaN) layer serving as a barrier layer.Type: GrantFiled: April 20, 2005Date of Patent: September 18, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Wataru Saito, Ichiro Omura
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Publication number: 20070210350Abstract: A power semiconductor device includes: a semiconductor layer having a trench extending along a first direction in a stripe configuration; a gate electrode buried in the trench for controlling a current flowing in the semiconductor layer; and a gate plug made of a material having higher electrical conductivity than the gate electrode, the gate plug having the stripe configuration and being connected to the gate electrode along the first direction. The semiconductor layer includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type provided partially in an upper face of the first semiconductor layer; a third semiconductor layer of the first conductivity type provided partially on the second semiconductor layer; and a fourth semiconductor layer of the second conductivity type provided on a lower face of the first semiconductor layer.Type: ApplicationFiled: March 6, 2007Publication date: September 13, 2007Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Ichiro Omura, Yoko Sakiyama, Hideki Nozaki, Atsushi Murakoshi, Masanobu Tsuchitani, Koichi Sugiyama, Tsuneo Ogura, Masakazu Yamaguchi, Tatsuo Naijo
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Patent number: 7250641Abstract: The nitride semiconductor device according to one embodiment of the present invention comprises: a silicon substrate; a first aluminum gallium nitride (AlxGa1?xN (0?x?1)) layer formed as a channel layer on the silicon substrate in an island shape; and a second aluminum gallium nitride (AlyGa1?yN (0?y?1, x<y)) layer formed as a barrier layer of a first conductive type or i-type on the first aluminum gallium nitride layer.Type: GrantFiled: October 12, 2004Date of Patent: July 31, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Wataru Saito, Ichiro Omura
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Patent number: 7244974Abstract: A power semiconductor device includes a first semiconductor layer, a second semiconductor layer of a first conductivity type, first and second main electrodes, a control electrode and a third semi-conductor layer. The second semiconductor layer is formed on the first semiconductor layer. The first and second main electrodes are formed on the second semiconductor layer separately from each other. The control electrode is formed on the second semiconductor layer between the first and second main electrodes. The third semiconductor layer is formed on the second semiconductor layer between the control electrode and the second main electrode.Type: GrantFiled: July 28, 2005Date of Patent: July 17, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Wataru Saito, Ichiro Omura, Hiromichi Ohashi
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Patent number: 7238576Abstract: A semiconductor device comprises a drain layer of first conductivity type, drift layers of first and second conductivity types on the drain layer, an insulating film between the drift layers and contacting the drift layers, a first base layer of second conductivity type on a surface of the drift layer of first conductivity type, a source layer of first conductivity type selectively provided on a surface of the first base layer of second conductivity type, a gate insulating film on the first base layer of second conductivity type between the source layer and the drift layer, a gate electrode on the gate insulating film, a second base layer of second conductivity type on a surface of the drift layer, a first main electrode on the drain layer, and a second main electrode on the source layer, the first base layer and the second base layer.Type: GrantFiled: April 1, 2003Date of Patent: July 3, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Masakazu Yamaguchi, Ichiro Omura, Wataru Saito, Takashi Shinohe, Hiromichi Ohashi
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Publication number: 20070114570Abstract: A power semiconductor device includes trenches disposed in a first base layer of a first conductivity type at intervals to partition main and dummy cells, at a position remote from a collector layer of a second conductivity type. In the main cell, a second base layer of the second conductivity type, and an emitter layer of the first conductivity type are disposed. In the dummy cell, a buffer layer of the second conductivity type is disposed. A gate electrode is disposed, through a gate insulating film, in a trench adjacent to the main cell. A buffer resistor having an infinitely large resistance value is inserted between the buffer layer and emitter electrode. The dummy cell is provided with an inhibiting structure to reduce carriers of the second conductivity type to flow to and accumulate in the buffer layer from the collector layer.Type: ApplicationFiled: January 23, 2007Publication date: May 24, 2007Inventors: Masakazu Yamaguchi, Hideaki Ninomiya, Ichiro Omura, Tomoki Inoue
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Publication number: 20070114602Abstract: A semiconductor device includes: a first semiconductor layer of a first conductivity type; a first semiconductor region of the first conductivity type and a second semiconductor region of a second conductivity type alternately arranged in a lateral direction on the first semiconductor layer of the first conductivity type; a third semiconductor region of the second conductivity type formed on the first semiconductor region; a fourth semiconductor region of the first conductivity type formed on a portion of the surface of the third semiconductor region; a control electrode provided via an first insulating film in a groove formed in contact with the fourth semiconductor region, the third semiconductor region, and the first semiconductor region; a first main electrode electrically connected to the first semiconductor layer; a second main electrode forming a junction with the third and fourth semiconductor region; and a fifth semiconductor region of the second conductivity type.Type: ApplicationFiled: November 22, 2006Publication date: May 24, 2007Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Wataru Saito, Ichiro Omura
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Publication number: 20070040217Abstract: The power semiconductor device according to one embodiment of the present invention at least comprises: first pillar layers of the first conductive type and second pillar layers of a second conductive type which constitute a super-junction structure in a device section and which are arranged alternately in a horizontal direction, each of the first and second pillar layers having a column-shaped sectional structure; third pillar layers of the first conductive type and fourth pillar layers of the second conductive type which are adjacent to the super-junction structure of the device section to constitute another super-junction structure thinner in a vertical direction than the super-junction structure of the device section in a device termination section and which are arranged alternately in a horizontal direction, each of the third and fourth pillar layers having a column-shaped sectional structure; an outermost pillar layer which is stacked on one of the third or fourth pillar layers in the super-junction strType: ApplicationFiled: October 20, 2006Publication date: February 22, 2007Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Wataru Saito, Ichiro Omura
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Patent number: 7170106Abstract: A power semiconductor device includes trenches disposed in a first base layer of a first conductivity type at intervals to partition main and dummy cells, at a position remote from a collector layer of a second conductivity type. In the main cell, a second base layer of the second conductivity type, and an emitter layer of the first conductivity type are disposed. In the dummy cell, a buffer layer of the second conductivity type is disposed. A gate electrode is disposed, through a gate insulating film, in a trench adjacent to the main cell. A buffer resistor having an infinitely large resistance value is inserted between the buffer layer and emitter electrode. The dummy cell is provided with an inhibiting structure to reduce carriers of the second conductivity type to flow to and accumulate in the buffer layer from the collector layer.Type: GrantFiled: September 9, 2005Date of Patent: January 30, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Masakazu Yamaguchi, Hideaki Ninomiya, Ichiro Omura, Tomoki Inoue
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Publication number: 20070007537Abstract: A semiconductor device comprises: a first semiconductor layer of silicon carbide of a first conductivity type; a second semiconductor layer of silicon carbide of a second conductivity type selectively provided on the first semiconductor layer; a main electrode layer of silicon carbide of the first conductivity type selectively provided on the second semiconductor layer; a gate insulating film provided on the second semiconductor layer; a gate electrode formed on the gate insulating film; and a third semiconductor layer of the first conductivity type intervening a current path which is formed between the main electrode layer and the first semiconductor layer when an ON voltage is applied to the gate electrode. The third semiconductor layer is selectively provided on the first semiconductor layer and is adjacent to the second semiconductor layer. A doping density of the third semiconductor layer is higher than a doping density of the first semiconductor layer.Type: ApplicationFiled: July 3, 2006Publication date: January 11, 2007Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Tsuneo Ogura, Ichiro Omura
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Patent number: 7161209Abstract: The power semiconductor device according to one embodiment of the present invention at least comprises: first pillar layers of the first conductive type and second pillar layers of a second conductive type which constitute a super-junction structure in a device section and which are arranged alternately in a horizontal direction, each of the first and second pillar layers having a column-shaped sectional structure; third pillar layers of the first conductive type and fourth pillar layers of the second conductive type which are adjacent to the super-junction structure of the device section to constitute another super-junction structure thinner in a vertical direction than the super-junction structure of the device section in a device termination section and which are arranged alternately in a horizontal direction, each of the third and fourth pillar layers having a column-shaped sectional structure; an outermost pillar layer which is stacked on one of the third or fourth pillar layers in the super-junction strType: GrantFiled: October 12, 2004Date of Patent: January 9, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Wataru Saito, Ichiro Omura
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Patent number: 7157748Abstract: A nitride-based semiconductor device includes a first semiconductor layer consisting essentially of a nitride-based semiconductor, and a second semiconductor layer disposed on the first semiconductor layer and consisting essentially of a non-doped or first conductivity type nitride-based semiconductor. The first and second semiconductor layers forms a hetero-interface. A gate electrode is disposed on the second semiconductor layer. First and second trenches are formed in a surface of the second semiconductor layer at positions sandwiching the gate electrode. Third and fourth semiconductor layers of the first conductivity type are respectively formed in surfaces of the first and second trenches and each consist essentially of a diffusion layer having a resistivity lower than the first and second semiconductor layers. Source and drain electrodes are electrically connected to the third and fourth semiconductor layers, respectively.Type: GrantFiled: December 20, 2004Date of Patent: January 2, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Wataru Saito, Ichiro Omura
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Publication number: 20060289915Abstract: A semiconductor device comprises a semiconductor portion including first semiconductor layers of a first conduction type and second semiconductor layers of a second conduction type alternately arranged on the surface of a semiconductor substrate to form a striped shape. A main region is formed to arrange a main cell in a well. A current sense cell is arranged in a sense well. A sense region is formed having the direction of the length in a direction that intersects the direction of alternate arrangement of the first semiconductor layers and the second semiconductor layers.Type: ApplicationFiled: June 20, 2006Publication date: December 28, 2006Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Ichiro Omura, Wataru Saito
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Publication number: 20060284248Abstract: First semiconductor pillar layers of a first conduction type and second semiconductor pillar layers of a second conduction type are arranged on a first semiconductor layer of the first conduction type laterally, periodically and alternately at a first period to forma first pillar layer. Third semiconductor pillar layers of the first conduction type and fourth semiconductor pillar layers of the second conduction type are arranged on the first pillar layer laterally, periodically and alternately at a second period smaller than the first period to form a second pillar layer. A semiconductor base layer of the second conduction type is formed on a surface of the fourth semiconductor pillar layer. A semiconductor diffused layer of the first conduction type is formed on a surface of the semiconductor base layer.Type: ApplicationFiled: June 16, 2006Publication date: December 21, 2006Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Wataru Saito, Ichiro Omura
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Patent number: 7129692Abstract: A current detection equipment comprises a first coil and a second coil connected in series with the first coil. The current detection equipment is capable of detecting a current flowing through an object which is provided between the first and second coils or provided in a vicinity of the first or second coil. Each of the first and second coils having first conductive patterns provided on a surface of a substrate, a second conductive patterns provided on a back of the substrate and connecting parts which connect the first and second conductive patterns. A semiconductor device including the current detection equipment to measure the current flowing in a semiconductor element is also proposed.Type: GrantFiled: October 24, 2005Date of Patent: October 31, 2006Assignee: Kabushiki Kaisha ToshibaInventors: Ichiro Omura, Tomokazu Domon, Kazuya Kodani
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Publication number: 20060220156Abstract: The present semiconductor device comprises pillar layers formed on a first semiconductor layer, the pillar layers comprising a first semiconductor pillar layer of a first conductivity type and a second semiconductor pillar layer of a second conductivity type which are alternately formed in a first direction along a surface of the first semiconductor layer. A semiconductor base layer of the second conductivity type is selectively formed on the surface of the second semiconductor pillar layer. A guard ring layer of the second conductivity type is formed surrounding the outermost periphery of the semiconductor base layer. The semiconductor base layer has a smaller junction depth than the guard ring layer.Type: ApplicationFiled: February 22, 2006Publication date: October 5, 2006Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Wataru Saito, Ichiro Omura
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Patent number: 7115475Abstract: A method of manufacturing a semiconductor device in which a trench groove is formed in a first conductivity type semiconductor layer, and a second conductivity type semiconductor layer is epitaxially grown so as to bury the trench groove. The second conductivity type semiconductor layer is then removed until a surface of the first conductivity type semiconductor layer is exposed. The first conductivity type semiconductor layer is epitaxially grown on the first conductivity type semiconductor layer and the second conductivity type semiconductor layer such that the thickness of the first conductivity type semiconductor layer increases by a length which is substantially the same as a depth of the trench groove.Type: GrantFiled: December 3, 2004Date of Patent: October 3, 2006Assignee: Kabushiki Kaisha ToshibaInventors: Masakazu Yamaguchi, Wataru Saito, Ichiro Omura, Masaru Izumisawa