Abstract: A buffer circuit with driving current adjusting function is provided which may automatically set a driving current characteristics of a buffer to the most suitable value according to a system where the driving current is to be applied.

Abstract: A master-slice semiconductor integrated circuit device includes a substrate for an input/output circuit section, which is segmented into a plurality of segments during a master processing step. In a slice processing step, slice cells are formed, using different substrate segments. Input/output circuits are formed by respective slice cells so that desired different supply voltages can be applied to input/output circuits on different substrate segments.

Abstract: A memory cell for an associative storage memory device includes a transmission gate which is rendered conductive or non-conductive in response to a potential on a word line for transferring information between an information hold circuit and a bit line or between the information hold circuit and an inverted bit line. Match line are precharged to ground and supply potentials, respectively, and, thereafter, a retrieval circuit compares information on the bit line or inverted bit line with information held in the information hold circuit and produces a control signal to control the potentials on the match lines in accordance with the result of comparison. After the match lines are precharged, a gating circuit is rendered conductive in response to potentials on output control line and inverted output control line to thereby couple the control signal to the match lines.

Abstract: A master-slice semiconductor integrated circuit device includes a substrate for an input/output circuit section, which is segmented into a plurality of segments during a master processing step. In a slice processing step, slice cells are formed, using different substrate segments. Input/output circuits are formed by respective slice cells so that desired different supply voltages can be applied to input/output circuits on different substrate segments.

Abstract: A first output buffer having a large current driving capability and a second output buffer having a small current driving capability are connected in parallel between an input terminal and an external lead. The first and second output buffers each includes two CMOS inverters connected in series between the input terminal and the external lead. The P-channel and N-channel MOSFETs of the two CMOS inverters in the second output buffer have gate widths smaller than each of the P-channel and N-channel MOSFETs, respectively, of the two CMOS inverters in the first output buffer. Also disclosed is an output buffer having P-channel and N-channel MOSFETs arranged as a CMOS inverter, but with a base of a first bipolar transistor connected to a source of the N-channel MOSFET. An emitter of the first bipolar transistor is connected to ground and its collector is connected to an output of the output buffer.

Abstract: An extension directed integrated circuit device having a learning function on a Boltzmann model, includes a plurality of synapse representing units arrayed in a matrix, a plurality of neuron representing units, a plurality of educator signal control circuits, and a plurality of buffer circuits. Each synapse representing unit is connected to a pair of axon signal transfer lines and a pair of dendrite signal transfer lines. Each synapse representing unit includes a learning control circuit which derives synapse load change value data in accordance with predetermined learning rules in response to a first axon signal Si and a second axon signal Sj, a synapse load representing circuit which corrects a synapse load in response to the synapse load change valued data and holds the corrected synapse load value Wij, a first synapse coupling operating circuit which derives a current signal indicating a product Wij.multidot.

Abstract: An extension directed integrated circuit device having a learning function on a Boltzmann model, includes a plurality of synapse representing units arrayed in a matrix to form a rectangle including a first and second triangles on a semiconductor chip, a plurality of neuron representing units and a plurality of educator signal control circuits which are arranged along first and second sides of the rectangle, and a plurality of buffer circuits arranged along third and fourth sides of the rectangle. The first side is opposite to the third side, and the second side is opposite to the fourth side. Axon signal transfer lines and dendrite signal lines are so arranged that the neuron representing units are full-connected in each of the first right triangle the second right triangle. Alternatively, axon signal lines and dendrite signal ines are arranged in parallel with rows and columns of the synapse representing unit matrix, so that the neuron representing units are full-connected in the rectangle.

Abstract: In a circuit for testing integrated circuit devices, scan registers (8.about.16) and data selecting circuits (20-28) are connected between a plurality of circuit blocks (29.about.31) in correspondence with the number of bits of the data, with the scan registers connected to each other by a shift register path so as to have a function of one shift register as a whole. A register selecting circuit (20.about.28) is connected to a clock input terminal (T1, T2) of the scan register. The scan registers other than those corresponding to the logic circuit block to be tested are selected by the register selecting circuit. Consequently, clocks for scanning scan registers other than those provided before and after the required circuit block are eliminated, enabling reduction of time required for scan test.

Abstract: An internal logic gate portion (3) is provided in the central portion of a semiconductor chip (1), input/output buffers (4) are provided to surround the internal logic gate portion (3), and bonding pads (2) are provided in the peripheral portions of the semiconductor chip (1) corresponding to input/output buffer cells (5) in the input/output buffer. Each of the input/output buffer cells (5) comprises an output P-MOS portion (6), an output N-MOS portion (7), an input/logic P-MOS portion (8) and an input/logic N-MOS portion (9), which are respectively arranged in a single line in the direction from the bonding pads (2) to the internal logic gate portion (3). In the above described structure, the size of each of the input/output buffer cells (5) in the pad arranging direction of the bonding pads (2) is decreased, so that the number of input/output pins can be increased according to the decreased use of space in the pad arranging direction required by each input/output buffer cell (5).

Abstract: An inverter circuit (I.sub.3) is disclosed which includes a P-channel MOSFET (3) and a N-channel MOSFET (4) connected in series between a power supply (V.sub.DD) and a ground (GND). The inverter circuit further includes a P-channel MOSFET (5) and a N-channel MOSFET (6) connected in parallel between the gates of the FETs (3) and (4). The FETs (3) and (4) have their gates connected to receive testing mode signals (T.sub.E). In a testing mode operation, the FET (6) is rendered conductive to allow an input signal to be applied to the gate of the FET (4) through the FET (6). The FET (4), having an on-resistance lower than the FET (3), is driven into conduction in response to the output signal applied through the FET (6), thereby providing a slowly rising output signal. The slow rising output signal is free from undershoot or ringing.

Abstract: A semiconductor integrated circuit includes cascaded asynchronous sequential logic circuits. Scanning shift registers are provided between the asynchronous sequential circuits to permit test data to be applied to the inputs of the circuits and to latch and shift out output data provided by the circuits in response to the test data. Additional gating circuitry is provided between the scanning shift registers and the inputs of the asynchronous sequential circuits to prevent new data latched into the scanning shift register from causing the asynchronous sequential circuit connected to the scanning shift register output from changing state during testing. This same additional circuitry may be used to provide pulses of controlled width and/or timing to asynchronous sequential circuit inputs in response to externally generated gating control signals.

Abstract: A semiconductor integrated circuit device for transmitting data between a plurality of circuit blocks at least one thereof including a sequential circuit and enabling the circuit blocks to test in a scan testing type which has a plurality of scan registers provided between the plurality of circuit blocks corresponding to the number of bits of data to be transmitted for outputting the output data of the previous stage circuit block as it is at ordinary operating time and for holding and outputting the output data of the previous circuit block or test data for scan test synchronously with an external clock at testing time so that the circuits are connected by a shift register pass in such a manner that the entirety has one shaft register function, and a latch circuit provided at its data input terminal to the data output terminal of the corresponding scan register for outputtting the output data of the corresponding scan register as it is to the circuit block of next stage at ordinary operation time and holding

Abstract: A test circuit of a semiconductor integrated circuit apparatus comprising a latch circuit connected to an output terminal of a scan register for holding output data of the scan register stored before scanning in a scan mode during the test operation.

Abstract: A semiconductor integrated circuit device includes a plurality of latch circuits which are provided between adjacent circuit blocks. Each latch circuit functions to transfer output data from a preceding circuit block directly to a subsequent circuit block during a normal operation of the circuit device, to hold the output data until a scanning of associated scan register and supply them to the subsequent circuit block in a scan mode of a test operation and to hole the output data while outputting them in synchronism with an external clock in a test mode of the test operation.

Abstract: A method of reconstructing or reclaiming river channels which are partially filled with soft, slimy sedimentary deposits including industrial wastes which are in a semi-fluid condition or fluidized state comprising the steps of: demarcating a portion of the channel by placing a water tight wall entirely across the channel from bank to bank at an upstream and downstream location; depositing stable fill material adjacent the banks of the channel so as to displace the soft sedimentary deposits and water toward the center of the channel; and treating the displaced soft sedimentary deposit in situ beneath the overlying water so as to stabilize the entire mass.The channel may be completely reclaimed by pumping out the overlying water after the soft sedimentary deposit has been stabilized and then filling with stable material or stable material may be simply placed on the stabilized mass and the water displaced over the top of the downstream wall or over the adjacent bank.