Patents by Inventor Ichiro Uehara
Ichiro Uehara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240102142Abstract: A spray coating containing a rare earth fluoride and/or a rare earth acid fluoride contains carbon at 0.01-2% by mass or titanium or molybdenum at 1-1000 ppm. When an acid fluoride is not contained, the spray coating is gray to black in which, in terms of the L*a*b* chromaticity, L* is 25-64, a* is ?3.0 to +5.0, and b* is ?4.0 to +8.0. When an acid fluoride is contained, the spray coating is white or gray to black in which, in terms of the L*a*b* chromaticity, L* is equal to or greater than 25 and less than 91, a* is ?3.0 to +5.0, and b* is ?6.0 to +8.0. By forming this coating on a plasma resistant member, a partial color change is reduced, thus, a member that is capable of reliably realizing the original longevity is obtained.Type: ApplicationFiled: November 22, 2023Publication date: March 28, 2024Applicant: Shin-Etsu Chemical Co., Ltd.Inventors: Noriaki Hamaya, Ichiro Uehara
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Publication number: 20200002799Abstract: A spray coating containing a rare earth fluoride and/or a rare earth acid fluoride contains, carbon at 0.01-2% by mass or titanium or molybdenum at 1-1000 ppm. When an acid fluoride is not contained, the spray coating is gray to black in which, in terms of the L*a*b* chromaticity, L* is 25-64, a* is ?3.0 to +5.0, and b* is ?4.0 to +8.0. When an acid fluoride is contained, the spray coating is white or gray to black in which, in terms of the L*a*b* chromaticity, L* is equal to or greater than 25 and less than 91, a* is ?3.0 to +5.0, and b* is ?6.0 to +8.0. By forming this coating on a plasma resistant member, a partial color change is reduced, thus, a member that is capable of reliably realizing the original longevity is obtained.Type: ApplicationFiled: February 28, 2018Publication date: January 2, 2020Applicant: Shin-Etsu Chemical Co., Ltd.Inventors: Noriaki HAMAYA, Ichiro UEHARA
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Patent number: 9263503Abstract: In an EL element having an anode, an insulating film (bump) formed on the anode, and an EL film and a cathode formed on the insulating film, each of a bottom end portion and a top end portion of the insulating film is formed so as to have a curved surface. The taper angle of a central portion of the insulating film is set within the range from 35° to 70°, thereby preventing the gradient of the film forming surface on which the EL film and the cathode are to be formed from being abruptly changed. On the thus-formed film forming surface, the EL film and the cathode can be formed so as to be uniform in thickness, so that occurrence of discontinuity in each of EL film and the cathode is prevented.Type: GrantFiled: December 30, 2013Date of Patent: February 16, 2016Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Hideomi Suzawa, Ichiro Uehara
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Patent number: 9142596Abstract: In an EL element having an anode, an insulating film (bump) formed on the anode, and an EL film and a cathode formed on the insulating film, each of a bottom end portion and a top end portion of the insulating film is formed so as to have a curved surface. The taper angle of a central portion of the insulating film is set within the range from 35° to 70°, thereby preventing the gradient of the film forming surface on which the EL film and the cathode are to be formed from being abruptly changed. On the thus-formed film forming surface, the EL film and the cathode can be formed so as to be uniform in thickness, so that occurrence of discontinuity in each of EL film and the cathode is prevented.Type: GrantFiled: December 30, 2013Date of Patent: September 22, 2015Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Hideomi Suzawa, Ichiro Uehara
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Publication number: 20140183576Abstract: In an EL element having an anode, an insulating film (bump) formed on the anode, and an EL film and a cathode formed on the insulating film, each of a bottom end portion and a top end portion of the insulating film is formed so as to have a curved surface. The taper angle of a central portion of the insulating film is set within the range from 35° to 70°, thereby preventing the gradient of the film forming surface on which the EL film and the cathode are to be formed from being abruptly changed. On the thus-formed film forming surface, the EL film and the cathode can be formed so as to be uniform in thickness, so that occurrence of discontinuity in each of EL film and the cathode is prevented.Type: ApplicationFiled: December 30, 2013Publication date: July 3, 2014Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Hideomi Suzawa, Ichiro Uehara
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Patent number: 8618732Abstract: In an EL element having an anode, an insulating film (bump) formed on the anode, and an EL film and a cathode formed on the insulating film, each of a bottom end portion and a top end portion of the insulating film is formed so as to have a curved surface. The taper angle of a central portion of the insulating film is set within the range from 35° to 70°, thereby preventing the gradient of the film forming surface on which the EL film and the cathode are to be formed from being abruptly changed. On the thus-formed film forming surface, the EL film and the cathode can be formed so as to be uniform in thickness, so that occurrence of discontinuity in each of EL film and the cathode is prevented.Type: GrantFiled: April 15, 2013Date of Patent: December 31, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Hideomi Suzawa, Ichiro Uehara
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Publication number: 20130285062Abstract: In an EL element having an anode, an insulating film (bump) formed on the anode, and an EL film and a cathode formed on the insulating film, each of a bottom end portion and a top end portion of the insulating film is formed so as to have a curved surface. The taper angle of a central portion of the insulating film is set within the range from 35° to 70°, thereby preventing the gradient of the film forming surface on which the EL film and the cathode are to be formed from being abruptly changed. On the thus-formed film forming surface, the EL film and the cathode can be formed so as to be uniform in thickness, so that occurrence of discontinuity in each of EL film and the cathode is prevented.Type: ApplicationFiled: April 15, 2013Publication date: October 31, 2013Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei YAMAZAKI, Hideomi SUZAWA, Ichiro UEHARA
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Patent number: 8421352Abstract: In an EL element having an anode, an insulating film (bump) formed on the anode, and an EL film and a cathode formed on the insulating film, each of a bottom end portion and a top end portion of the insulating film is formed so as to have a curved surface. The taper angle of a central portion of the insulating film is set within the range from 35° to 70°, thereby preventing the gradient of the film forming surface on which the EL film and the cathode are to be formed from being abruptly changed. On the thus-formed film forming surface, the EL film and the cathode can be formed so as to be uniform in thickness, so that occurrence of discontinuity in each of EL film and the cathode is prevented.Type: GrantFiled: February 4, 2011Date of Patent: April 16, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Hideomi Suzawa, Ichiro Uehara
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Patent number: 8420546Abstract: In the manufacturing method of a GOLD structured TFT having a gate electrode of double-layered structure, in which, compared to a second layer gate electrode, the first layer gate electrode is thinner in film thickness and longer in dimension of the channel direction, by controlling the density of the photo-absorbent contained in a positive type resist such as diazonaphthoquinone (DNQ)-novolac resin series, the taper angle of the side wall is controlled to a desired angle range so that the angle thereof becomes smaller. Owing to this, it is possible to control the retreat amount of the resist when carrying out dry etching and the dimension of Lov, area to a desired dimensional range so that the dimension thereof becomes larger.Type: GrantFiled: September 6, 2006Date of Patent: April 16, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Ichiro Uehara, Hideomi Suzawa
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Patent number: 8324032Abstract: Formation of LDD structures and GOLD structures in a semiconductor device is conventionally performed in a self aligning manner with gate electrodes as masks, but there are many cases in which the gate electrodes have two layer structures, and film formation processes and etching processes become complex. Further, in order to perform formation of LDD structures and GOLD structures only by processes such as dry etching, the transistor structures all have the same structure, and it is difficult to form LDD structures, GOLD structures, and single drain structures separately for different circuits.Type: GrantFiled: June 3, 2011Date of Patent: December 4, 2012Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hideto Ohnuma, Ichiro Uehara
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Publication number: 20110294266Abstract: Formation of LDD structures and GOLD structures in a semiconductor device is conventionally performed in a self aligning manner with gate electrodes as masks, but there are many cases in which the gate electrodes have two layer structures, and film formation processes and etching processes become complex. Further, in order to perform formation of LDD structures and GOLD structures only by processes such as dry etching, the transistor structures all have the same structure, and it is difficult to form LDD structures, GOLD structures, and single drain structures separately for different circuits.Type: ApplicationFiled: June 3, 2011Publication date: December 1, 2011Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Hideto Ohnuma, Ichiro Uehara
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Patent number: 8044588Abstract: In an EL element having an anode, an insulating film (bump) formed on the anode, and an EL film and a cathode formed on the insulating film, each of a bottom end portion and a top end portion of the insulating film is formed so as to have a curved surface. The taper angle of a central portion of the insulating film is set within the range from 35° to 70°, thereby preventing the gradient of the film forming surface on which the EL film and the cathode are to be formed from being abruptly changed. On the thus-formed film forming surface, the EL film and the cathode can be formed so as to be uniform in thickness, so that occurrence of discontinuity in each of EL film and the cathode is prevented.Type: GrantFiled: April 1, 2009Date of Patent: October 25, 2011Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Hideomi Suzawa, Ichiro Uehara
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Publication number: 20110133635Abstract: In an EL element having an anode, an insulating film (bump) formed on the anode, and an EL film and a cathode formed on the insulating film, each of a bottom end portion and a top end portion of the insulating film is formed so as to have a curved surface. The taper angle of a central portion of the insulating film is set within the range from 35° to 70°, thereby preventing the gradient of the film forming surface on which the EL film and the cathode are to be formed from being abruptly changed. On the thus-formed film forming surface, the EL film and the cathode can be formed so as to be uniform in thickness, so that occurrence of discontinuity in each of EL film and the cathode is prevented.Type: ApplicationFiled: February 4, 2011Publication date: June 9, 2011Inventors: Shunpei Yamazaki, Hideomi Suzawa, Ichiro Uehara
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Patent number: 7955912Abstract: Formation of LDD structures and GOLD structures in a semiconductor device is conventionally performed in a self aligning manner with gate electrodes as masks, but there are many cases in which the gate electrodes have two layer structures, and film formation processes and etching processes become complex. Further, in order to perform formation of LDD structures and GOLD structures only by processes such as dry etching, the transistor structures all have the same structure, and it is difficult to form LDD structures, GOLD structures, and single drain structures separately for different circuits.Type: GrantFiled: June 25, 2010Date of Patent: June 7, 2011Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hideto Ohnuma, Ichiro Uehara
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Publication number: 20100261320Abstract: Formation of LDD structures and GOLD structures in a semiconductor device is conventionally performed in a self aligning manner with gate electrodes as masks, but there are many cases in which the gate electrodes have two layer structures, and film formation processes and etching processes become complex. Further, in order to perform formation of LDD structures and GOLD structures only by processes such as dry etching, the transistor structures all have the same structure, and it is difficult to form LDD structures, GOLD structures, and single drain structures separately for different circuits.Type: ApplicationFiled: June 25, 2010Publication date: October 14, 2010Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Hideto Ohnuma, Ichiro Uehara
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Patent number: 7799515Abstract: In a resist pattern forming method in which bake processing is performed at a temperature not lower than a glass transition temperature in order to obtain the desired sidewall angle, resist removable is difficult. Accordingly, in the resist pattern forming method of performing bake processing at a temperature not lower than a glass transition temperature, a process margin for resist removability cannot be ensured, so that there is the problem that it is impossible to compatibly realize both the formation of a resist pattern having the desired sidewall angle and the resist removability of the resist pattern. The invention aims to solve the problem. A resist pattern including a diazonaphthoquinone (DNQ)-novolac resin type of positive resist is formed, and the resist pattern is irradiated with light within the range of photosensitive wavelengths of a DNQ photosensitizer to perform bake processing on the resist pattern at a temperature not lower than the glass transition temperature of the resist pattern.Type: GrantFiled: January 18, 2008Date of Patent: September 21, 2010Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Masaharu Nagai, Ichiro Uehara
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Patent number: 7745271Abstract: Formation of LDD structures and GOLD structures in a semiconductor device is conventionally performed in a self aligning manner with gate electrodes as masks, but there are many cases in which the gate electrodes have two layer structures, and film formation processes and etching processes become complex. Further, in order to perform formation of LDD structures and GOLD structures only by processes such as dry etching, the transistor structures all have the same structure, and it is difficult to form LDD structures, GOLD structures, and single drain structures separately for different circuits.Type: GrantFiled: January 4, 2008Date of Patent: June 29, 2010Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hideto Ohnuma, Ichiro Uehara
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Patent number: 7655328Abstract: An electrically conductive, plasma-resistant member adapted for exposure to a halogen-based gas plasma atmosphere includes a substrate having formed on at least part of a region thereof to be exposed to the plasma a thermal spray coating composed of yttrium metal or yttrium metal in admixture with yttrium oxide and/or yttrium fluoride so as to confer electrical conductivity. Because the member is conductive and has an improved erosion resistance to halogen-based corrosive gases or plasmas thereof, particle contamination due to plasma etching when used in semiconductor manufacturing equipment or flat panel display manufacturing equipment can be suppressed.Type: GrantFiled: April 19, 2007Date of Patent: February 2, 2010Assignee: Shin-Etsu Chemical Co., Ltd.Inventors: Takao Maeda, Yuuichi Makino, Hajime Nakano, Ichiro Uehara
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Publication number: 20090243464Abstract: In an EL element having an anode, an insulating film (bump) formed on the anode, and an EL film and a cathode formed on the insulating film, each of a bottom end portion and a top end portion of the insulating film is formed so as to have a curved surface. The taper angle of a central portion of the insulating film is set within the range from 35° to 70°, thereby preventing the gradient of the film forming surface on which the EL film and the cathode are to be formed from being abruptly changed. On the thus-formed film forming surface, the EL film and the cathode can be formed so as to be uniform in thickness, so that occurrence of discontinuity in each of EL film and the cathode is prevented.Type: ApplicationFiled: April 1, 2009Publication date: October 1, 2009Inventors: Shunpei Yamazaki, Hideomi Suzawa, Ichiro Uehara
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Patent number: RE43471Abstract: In a patterning process of a semiconductor device having inverted stagger type TFTs, a normal photolithography step using diazo naphthoquinone (DNQ)-Novolac resin based positive photo resist is applied, and a problem of the area dependency of the photo resist pattern side wall taper angle may occur. The problem is critical for the reason of influence on variation of an etching shape in a dry-etching step. The present invention has an object to solve the above problem. In a photolithography step, which is patterning step of a semiconductor device having inverted stagger type TFTs, by adjusting a pre-bake temperature or a PEB (post-exposure-bake) temperature, and positively performing evacuation of solvent in a state of a photo resist film, the volume contraction by evacuation of solvent at the post-bake is reduced, and the problem of the area dependency of the photo resist pattern side wall taper angle is solved, which is deformation due to the volume contraction.Type: GrantFiled: October 8, 2004Date of Patent: June 12, 2012Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Ichiro Uehara, Kazuhiro Toshima, Shunpei Yamazaki