Patents by Inventor Ichirou Nakayama

Ichirou Nakayama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20010037939
    Abstract: A sample table for holding a silicon substrate into which an impurity is introduced is provided in the lower portion of a vacuum chamber. A high frequency power source is connected to the sample table through a coupling capacitor. The high frequency power source has a self-bias of 500 V, for example. Gas introducing means for introducing a sputtering gas such as an argon gas is provided on the bottom of the vacuum chamber. A solid target which contains an impurity which should be introduced, for example, boron is provided in the upper portion of the vacuum chamber.
    Type: Application
    Filed: August 7, 1996
    Publication date: November 8, 2001
    Applicant: Hiroaki Nakaoka
    Inventors: HIROAKI NAKAOKA, BUNJI MIZUNO, MICHIHIKO TAKASE, ICHIROU NAKAYAMA
  • Patent number: 6169004
    Abstract: A P-type impurity layer, a silicon monocrystal film, a silicon oxide film and a crystal silicon film are successively formed on a semiconductor substrate by introducing appropriate functional gases on the semiconductor substrate, while irradiating the semiconductor substrate with ionizing radiation or light at a temperature lower than 250° C. After forming a photoresist on the crystal silicon film at a temperature lower than 250° C., the resultant semiconductor substrate is subjected to etching by using the photoresist as a mask, so as to form a gate electrode B out of the silicon oxide film and a gate insulating film out of the silicon oxide film. Then, the resultant semiconductor substrate is subjected to etching again by using the gate electrode as a mask, so as to form a channel region out of the P-type impurity layer. A source electrode and a drain electrode are formed on the respective sides of the gate electrode on the semiconductor substrate by introducing an appropriate functional.
    Type: Grant
    Filed: June 9, 1998
    Date of Patent: January 2, 2001
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Bunji Mizuno, Kenji Okada, Ichirou Nakayama
  • Patent number: 5817559
    Abstract: A P-type impurity layer, a silicon monocrystal film, a silicon oxide film and a crystal silicon film are successively formed on a semiconductor substrate by introducing appropriate functional gases on the semiconductor substrate, while irradiating the semiconductor substrate with ionizing radiation or light at a temperature lower than 250.degree. C. After forming a photoresist on the crystal silicon film at a temperature lower than 250.degree. C., the resultant semiconductor substrate is subjected to etching by using the photoresist as a mask, so as to form a gate electrode B out of the silicon oxide film and a gate insulating film out of the silicon oxide film. Then, the resultant semiconductor substrate is subjected to etching again by using the gate electrode as a mask, so as to form a channel region out of the P-type impurity layer.
    Type: Grant
    Filed: May 15, 1995
    Date of Patent: October 6, 1998
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Bunji Mizuno, Kenji Okada, Ichirou Nakayama
  • Patent number: 5547294
    Abstract: A method and apparatus for controlling a serial printer of the invention selects a first digit character by counting a predetermined number of timing pulses that starts to be generated during carriage return and sets the predetermined number so as to correspond to the character to be printed and the number of digits printed in a last line. The apparatus may include a time measuring device, and selects a first digit character to be printed in succession to a last line by measuring a predetermined carriage return time and sets the predetermined carriage return time so as to correspond to the character to be printed and the number of digits printed in the last line. The apparatus also may include a timing pulse interval detector, and a first digit character is selected after the selection of a character group by counting a predetermined number of timing pulses and the predetermined number is set so as to correspond to the character to be printed and the number of digits printed in the last line.
    Type: Grant
    Filed: December 21, 1992
    Date of Patent: August 20, 1996
    Assignee: Seiko Epson Corporation
    Inventors: Ichirou Nakayama, Masami Ookawa