Abstract: Test structures and alignment marks enable accurate measurements of alignment in the active area of an image sensor device. The alignment marks are formed in the active area replacing pixels near the lithographic shot boundaries of the array. Misalignment across the lithographic shots is assessed through the degree of shifting between the alignment patterns. The alignment marks are located in a pixel location of the active area and can measure the actual lithographic shot-to-shot misalignment in the active area, which can be used to make an accurate lithographic alignment. Having such alignment marks allows for a more accurate assessment of the in-line process manufacturing capability as well as a more rapid feedback of in-array drift, which would allow a faster and better control for yield loss.

Abstract: An image sensor array includes pixels arranged in rows and columns, wherein each pixel includes a transistor serially coupled to a photodiode, data lines coupled to a first node of the pixel, bias lines coupled to a second node of the pixel, gate lines coupled to a third node of the pixel, and electrostatic-discharge (ESD) circuits coupled between the gate lines and an ESD bus, wherein the ESD circuits each include first and second metal oxide offset bottom gate transistors in parallel connection.

Abstract: An image sensor includes a substrate, a thin film transistor on the substrate, a dielectric layer over the thin film transistor, a stacked metal layer on and extending through the dielectric layer to the thin film transistor, a bulk heterojunction layer directly coupled to the stacked metal layer, either a hole transport layer directly coupled to the bulk heterojunction layer, and a top contact layer directly coupled to the hole transport layer, or a top contact layer directly coupled to the bulk heterojunction layer. The bulk heterojunction layer includes an electron donor/acceptor material, the hole transport layer includes a transparent conductive polymer material, and the top contact layer includes a transparent conductive material. The image sensor includes a moisture barrier layer directly coupled to the top contact layer, including an optically clear adhesive and a laminated transparent barrier film.

Abstract: An image sensor includes a substrate, a thin film transistor on the substrate, a dielectric layer over the thin film transistor, a stacked metal layer on and extending through the dielectric layer to the thin film transistor, a bulk heterojunction layer directly coupled to the stacked metal layer, either a hole transport layer directly coupled to the bulk heterojunction layer, and a top contact layer directly coupled to the hole transport layer, or a top contact layer directly coupled to the bulk heterojunction layer. The bulk heterojunction layer includes an electron donor/acceptor material, the hole transport layer includes a transparent conductive polymer material, and the top contact layer includes a transparent conductive material. The image sensor includes a moisture barrier layer directly coupled to the top contact layer, including an optically clear adhesive and a laminated transparent barrier film.

Abstract: An image sensor array includes pixels arranged in rows and columns, wherein each pixel includes a transistor serially coupled to a photodiode, data lines coupled to a first node of the pixel, bias lines coupled to a second node of the pixel, gate lines coupled to a third node of the pixel, and electrostatic-discharge (ESD) circuits coupled between the gate lines and an ESD bus, wherein the ESD circuits each include first and second metal oxide offset bottom gate transistors in parallel connection.

Abstract: An ESD circuit includes a first metal oxide channel device having a drain coupled to a first node, a source coupled to a second node, and a gate coupled to the first node; a second metal oxide channel device having a source coupled to the first node, a drain coupled to the second node, and a gate coupled to the second node; a first capacitor coupled between the first and second nodes proximate to the first metal oxide channel device; and a second capacitor coupled between the first and second nodes proximate to the second metal oxide channel device. The ESD circuit can further include a third capacitor coupled between the first and second nodes proximate to the first capacitor. The ESD circuit can further include a fourth capacitor coupled between the first and second nodes proximate to the second capacitor.

Abstract: A test structure for characterizing an organic photodiode image sensor includes, on a common substrate, a cathode sheet resistance portion; a diode capacitance portion; an organic photodiode sheet resistance portion; a contact resistance portion; a step coverage portion; a quantum efficiency portion; a film adhesion portion; and an inkjet printing portion. The organic photodiode sheet resistance portion includes gate metal sets, each gate metal set including four evenly spaced metal lines terminating in a probe point, wherein the spacing within each gate metal set is progressively increased from a first gate metal set to a last gate metal set, and wherein a spacing between each gate metal set is larger than the spacing within any gate metal set; and an organic photodiode sheet formed over the gate metal sets.

Abstract: Test structures and alignment marks enable accurate measurements of alignment in the active area of an image sensor device. The alignment marks are formed in the active area replacing pixels near the lithographic shot boundaries of the array. Misalignment across the lithographic shots is assessed through the degree of shifting between the alignment patterns. The alignment marks are located in a pixel location of the active area and can measure the actual lithographic shot-to-shot misalignment in the active area, which can be used to make an accurate lithographic alignment. Having such alignment marks allows for a more accurate assessment of the in-line process manufacturing capability as well as a more rapid feedback of in-array drift, which would allow a faster and better control for yield loss.

Abstract: An ESD circuit includes a first metal oxide channel device having a drain coupled to a first node, a source coupled to a second node, and a gate coupled to the first node; a second metal oxide channel device having a source coupled to the first node, a drain coupled to the second node, and a gate coupled to the second node; a first capacitor coupled between the first and second nodes proximate to the first metal oxide channel device; and a second capacitor coupled between the first and second nodes proximate to the second metal oxide channel device. The ESD circuit can further include a third capacitor coupled between the first and second nodes proximate to the first capacitor. The ESD circuit can further include a fourth capacitor coupled between the first and second nodes proximate to the second capacitor.

Abstract: A test structure for characterizing an organic photodiode image sensor includes, on a common substrate, at least one of a cathode sheet resistance portion; a diode capacitance portion; an OPD sheet resistance portion; a contact resistance portion; a step coverage portion; a quantum efficiency portion; a film adhesion portion; and an inkjet printing portion.

Abstract: A multi-display apparatus includes two panels disposed with a step difference so that pixel boundaries of display devices formed on substrates overlap, and at least one of the two panels includes a thin film encapsulation layer covering the display device and disposed on an adjacent surface of one of the two panels where there is the step difference to improve a disconnection of an image at a seam between the two panels, and mitigate a perspective difference of the image at the seam due to the step difference between the two panels, thereby realizing a large natural and smooth image.

Abstract: A multi-display apparatus includes a thin film encapsulating structure to prevent moisture penetration through sides of the encapsulating structure. Each of a plurality of unit panels of the multi-display apparatus includes a substrate, a display device formed on the substrate, an organic material layer formed on the substrate to bury the display device, an inorganic material layer stacked on the organic material layer, and a moisture barrier wall that is formed outside the display device on the substrate and has a height greater than a thickness of the organic material layer. The multi-display apparatus having a thin film encapsulating structure can realize a stable, smooth, and large image screen since the thin film encapsulating structure can reduce a width of seams between the unit panels and can prevent moisture penetration.

Abstract: A flat panel display device includes a display area in which a desired image is displayed, and a non-display area arranged outside the display area and bordering the display area, and further includes bank portions arranged in a pattern in the display area and partitioning a plurality of first openings, emission elements arranged at the first openings, dummy bank portions formed in the non-display area in substantially a same pattern as the bank portions and partitioning a plurality of second openings, an absorbing material layer for removing oxygen/moisture located at the second openings, and a sealing passivation layer isolating the emission elements from the outside air and including a structure having at least two layers comprising an organic film and an inorganic film deposited alternately. Thus, the emission elements are prevented from being oxidized or corroded by a harmful material, and in a manner that minimizes additional processes.

Abstract: Disclosed is a method of manufacturing a thin film transistor, in which a semiconductor layer and a gate insulating film may be formed through ink jet printing using a single bank, thereby simplifying the manufacturing process and decreasing the manufacturing cost, leading to more economical thin film transistors. The thin film transistor manufactured using the method of example embodiments may be used as a switching element for sensors, memory devices, optical devices, and active matrix flat panel displays.

Abstract: A flat panel display device comprises a substrate, an organic light emitting diode formed on the substrate, an inner stack encapsulating the light emitting diode and comprising at least one organic layer and one inorganic layer, and an outer stack deposited to cover the inner stack and comprising at least two polymer layers and an adhesive and bonding layer disposed therebetween to combine the at least two polymer layers and a polymer heat-curing film disposed at an interface of each of the polymer layers and the adhesive and bonding layer and cured by heat treatment. According to the present invention, the flat panel display device and a manufacturing method for the same reliably seals the organic light emitting device and prevents degradation by permeation of external harmful materials, while providing high flexibility and low manufacturing cost.

Abstract: An organic light emitting display including an ultraviolet protecting layer and a method of manufacturing the same include a lower substrate; an ultraviolet hardening adhesive formed on the lower substrate; a driving unit and a light emitting unit deposited on the lower substrate and surrounded by the ultraviolet hardening adhesive; an encapsulation layer covering the driving unit and light emitting unit and preventing moisture and oxygen penetration from an outside; an upper substrate arranged on the encapsulation layer facing the lower substrate and fixed by the ultraviolet hardening adhesive; and an ultraviolet ray blocking film formed in a region to block the driving unit and the light emitting unit from being irradiated by UV rays radiated to harden the ultraviolet hardening adhesive. The ultraviolet ray blocking film is disposed in the encapsulation layer or on the upper substrate to protect the driving unit and light emitting unit from ultraviolet rays.

Abstract: An organic electroluminescent device having an improved structure includes; a duo-bank defining a unit pixel on a substrate, the duo-bank including a first bank and a second bank which are spaced apart from each other, and an organic luminescent material layer formed by inkjet printing a solution containing an organic luminescent material in the unit pixel and a gap between the first bank and the second bank.

Abstract: An organic electro luminescence device includes a light emission unit disposed on a substrate and a passivation film including a plurality of organic films and a plurality of inorganic films, the plurality of organic films and the plurality of inorganic films are alternately stacked to cover the light emission unit on the substrate, wherein a side of the passivation film disposed between an edge of the substrate and an edge of the light emission unit is gradually thinner from the edge of the light emission unit towards the edge of the substrate.

Abstract: An organic light emitting display and a manufacturing method thereof include an improved encapsulation layer. The encapsulation layer of the organic light emitting display includes an organic layer uniformly covering bank portions and light emitting areas on a substrate; and an inorganic layer formed thicker on the light emitting areas than on the bank portions. In the organic light emitting display, the inorganic layer is thick on the light emitting area in which a sealing ability is required and the bank portion is thin in order to provide flexibility. Therefore, the encapsulation layer can be formed more easily compared to an encapsulation layer on a device in which the organic layer and inorganic layer are alternately formed at least 10 times.

Abstract: Disclosed is a method for manufacturing an electrode of an electrochromic display. The method includes, prior to forming a porous nanoelectrode, forming a barrier rib for separating an electrolyte using a photosensitive paste as a material for the barrier rib, in which the photosensitive paste enables formation of patterns through a photolithographic process and maintains its shape at 450° C. to 500° C. The use of the electrode enables fabrication of an electrochromic display that is capable of preventing cross-talk between pixels and has advantages of fast response speed, prolonged lifespan upon repeated use and improved electrochromism, when compared to the case of metal oxide electrodes.