Patents by Inventor Iddo Carmon

Iddo Carmon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Parallel operating CPU core and DSP module for executing sequence of vector DSP code instructions to generate decoded constellation points in QAM/TCM modem application
    Patent number: 5625828
    Abstract: An integrated data processing system includes a shared internal bus for transferring both instructions and data. A shared bus interface unit is connected to the shared internal bus and connectable via a shared external bus to a shared external memory array such that instructions and data held in the shared external memory array are transferrable to the shared internal bus via the shared bus interface unit. A general purpose (GP) central processing unit (CPU) is connected to the shared internal bus for retrieving GP instructions. The GP CPU includes an execution unit for executing GP instructions to process data retrieved by the GP CPU from the shared internal bus. A digital signal processor (DSP) module connected to the shared internal bus, the DSP module includes a signal processor for processing an externally-provided digital signal received by the DSP module by executing DSP command-list instructions.
    Type: Grant
    Filed: July 1, 1994
    Date of Patent: April 29, 1997
    Assignee: National Semiconductor Corporation
    Inventors: Iddo Carmon, Itael Fraenkel, Omri Viner, Ronny Cohen
  • Integrated data processing system including CPU core and parallel, independently operating DSP module
    Patent number: 5592677
    Abstract: An integrated data processing system includes a shared internal bus for transferring both instructions and data. A shared bus interface unit is connected to the shared internal bus and connectable via a shared external bus to a shared external memory array such that instructions and data held in the shared external memory array are transferrable to the shared internal bus via the shared bus interface unit. A general purpose (GP) central processing unit (CPU) is connected to the shared internal bus for retrieving GP instructions. The GP CPU includes an execution unit for executing GP instructions to process data retrieved by the GP CPU from the shared internal bus. A digital signal processor (DSP) module connected to the shared internal bus, the DSP module includes a signal processor for processing an externally-provided digital signal received by the DSP module by executing DSP command-list instructions.
    Type: Grant
    Filed: May 19, 1994
    Date of Patent: January 7, 1997
    Assignee: National Semiconductor Corporation
    Inventors: Amos Intrater, Andy Birenbaum, Gideon Intrater, Iddo Carmon, Ilan Shimony, Itael Fraenkel, Lev Epstein, Lior Katzri, Omri Viner, Raya Levitan, Ronny Cohen, Sidi Yomtov, Yehezkel Tzadik, Zvi Greenfeld, Israel Greiss, Oved Oz, Yachin Afek, Meir Tsadik, Moshe Doron, Alberto Sandbank
  • Integrated CPU core and parallel, independently operating DSP module and time-critical core priority scheme
    Patent number: 5590357
    Abstract: An integrated data processing system includes a shared internal bus for transferring both instructions and data. A shared bus interface unit is connected to the shared internal bus and connectable via a shared external bus to a shared external memory array such that instructions and data held in the shared external memory array are transferrable to the shared internal bus via the shared bus interface unit. A general purpose (GP) central processing unit (CPU) is connected to the shared internal bus for retrieving GP instructions. The OP CPU includes an execution unit for executing GP instructions to process data retrieved by the GP CPU from the shared internal bus. A digital signal processor (DSP) module connected to the shared internal bus, the DSP module includes a signal processor for processing an externally-provided digital signal received by the DSP module by executing DSP command-list instructions.
    Type: Grant
    Filed: September 6, 1994
    Date of Patent: December 31, 1996
    Assignee: National Semiconductor Corporation
    Inventors: Amos Intrater, Andy Birenbaum, Gideon Intrater, Iddo Carmon, Ilan Shimony, Itael Fraenkel, Lev Epstein, Lior Katzri, Omri Viner, Raya Levitan, Ronny Cohen, Sidi Yomtov, Yehezkel Tzadik, Zvi Greenfeld, Israel Greiss, Oved Oz, Yachin Afek, Meir Tsadik, Moshe Doron, Alberto Sandbank
  • Integrated circuit having CPU and DSP for executing vector lattice propagation instruction and updating values of vector Z in a single instruction cycle
    Patent number: 5519879
    Abstract: An integrated data processing system includes a shared internal bus for transferring both instructions and data. A shared bus interface unit is connected to the shared internal bus and connectable via a shared external bus to a shared external memory array such that instructions and data held in the shared external memory array are transferrable to the shared internal bus via the shared bus interface unit. A general purpose (GP) central processing unit (CPU) is connected to the shared internal bus for retrieving GP instructions. The GP CPU includes an execution unit for executing GP instructions to process data retrieved by the GP CPU from the shared internal bus. A digital signal processor (DSP) module connected to the shared internal bus, the DSP module includes a signal processor for processing an externally-provided digital signal received by the DSP module by executing DSP command-list instructions.
    Type: Grant
    Filed: August 26, 1994
    Date of Patent: May 21, 1996
    Assignee: National Semiconductor Corporation
    Inventor: Iddo Carmon
  • Fine timing recovery for QAM modem receiver
    Patent number: 5200981
    Abstract: A QAM modem receiver performs fine-timing on a baseband signal sampled at two complex points per symbol. Based on this information, the algebraic signs of the second derivative of the baseband signal are estimated. These signs, computed separately for the real and imaginary axes, are used to a make local decision regarding convexity/concavity of the baseband signal. By accumulating these local decisions over an appropriate time interval, a global decision is reached regarding the sampling point position relative to the baseband signal maxima/minima. Based on this global decision, a correction command is issued to the modem's analog front end to either advance or delay the timing.
    Type: Grant
    Filed: June 22, 1992
    Date of Patent: April 6, 1993
    Assignee: National Semiconductor Corporation
    Inventor: Iddo Carmon