Abstract: A computer system uses power-consumption monitors for each of plural sets of devices. A power budget arbiter determines whether a collective power-consumption criterion is met at least in part as a function of said power-consumption data.

Abstract: A processor module includes an execution unit and a power monitor for monitoring power consumption by processor components including said execution unit.

Abstract: An interface module for interfacing an external device with a host computer is physically and electrically connected to the host computer. The module monitors its own power consumption and reports its power consumption to the host computer. This information can be used to determine the total power consumed by multiple modules, to indicate a problem with the interface module, or to detect a leakage current associated with the external device when main power is off.

Abstract: A memory module includes memory devices and a power tracker for monitoring power consumption by the memory devices. The power tracker generates digital power consumption data that can be stored and used to anticipate and/or diagnose of power-related problems. The invention allows accurate monitoring of conditions that could otherwise lead to failure and provides a source of diagnostic data in the event of system failure related to excessive power consumption. Modules that self-monitor power consumption can provide highly accurate data to the user and/or the system, which has significant advantages over error-prone theoretical measurements or estimations.

Abstract: A double-high memory system compatible with termination schemes for single-high memory systems. The system includes an interface for input and output of data. A plurality of memory units is configured in two rows. A transmission line couples the plurality of memory units and the interface. The double-high memory system is provided in a non-stacked arrangement.

Abstract: A circuit and system for improving signal integrity in a memory system. The circuit has a transmission line having a dampening impedance between a driver and a branch point of the transmission line. The circuit also has a termination impedance having one end coupled to the transmission line between the dampening impedance and the branch point. The transmission line has branches coupled to memory module interfaces. The branches have respective lengths between the branch point and the memory module interfaces to be configured symmetrically, wherein the branch point is at a point to balance signal transmission on the branches.

Abstract: A present invention termination stub system is disclosed. In one embodiment the termination stub system includes a first resistor, a division point, and a second resistor. The first resistor dampens reflections of a signal and is in series with an input signal path. The division point is coupled to the first resistor. The division point divides the signal into a plurality of output communication paths. The second resistor balances resistance of the termination stub system with a characteristic impedance of the signal input path. The second resistor is coupled to the first resistor in parallel with the input signal path and the plurality of output communication paths.

Abstract: A circuit and system addressing multiple computer memory modules on the same bus while maintaining proper timing. The circuit includes a transmission line having a dampening impedance between a driver and a branch point of the transmission line. The circuit also has a termination impedance having one end coupled to the transmission line between the dampening impedance and the branch point. The transmission line has branches from the branch point. Individual branches are coupled to at least one memory module interface.