Abstract: Reduced-power dynamic data circuits with wide-band energy recovery are described herein. In one embodiment, a circuit system comprises at least one sub-circuit in which at least one of the sub-circuits includes a capacitive output node that is driven between low and high states in a random manner for a time period and an inductive circuit path coupled to the capacitive output node. The inductive circuit path includes a transistor switch and an inductor connected in series to discharge and recharge the output node to a bias supply. A pulse generator circuit generates a pulse width that corresponds to a timing for driving the output node.

Abstract: Reduced-power dynamic data circuits with wide-band energy recovery are described herein. In one embodiment, a circuit system comprises at least one sub-circuit in which at least one of the sub-circuits includes a capacitive output node that is driven between low and high states in a random manner for a time period and an inductive circuit path coupled to the capacitive output node. The inductive circuit path includes a transistor switch and an inductor connected in series to discharge and recharge the output node to a bias supply. A pulse generator circuit generates a pulse width that corresponds to a timing for driving the output node.

Abstract: A circuit for recycling energy in bit lines (BL and BLB) of SRAM during write operation by (i) storing the charges BL and BLB to an intermediate voltage source (VLB) in a discharge phase and (ii) restoring the charges from the intermediate voltage, back to the BL or BLB in a recovery phase. The circuit includes an inductor, a pair of NMOS transistors, a series resonance node, and an energy source (VLB) in addition to the components of an SRAM input-output circuit shown as in FIG. 1. During the SRAM write operation, the BL or BLB is discharged to the energy source VLB through the pair of NMOS transistors and, the inductor and the series resonance node. The remaining energy in the BL and the BLB is discharged to ground using the write complementary write drivers.

Abstract: Disclosed is an auto-calibration circuit and method to generate the precise pulses that are required for energy savings achieved by using wide-band resonating cells for digital circuits. The calibration circuit performs a calibration technique by programming the number of PMOS devices and NMOS devices in parallel to an inverter, and these numbers are dynamically changed based on a target reference voltage that is defined by a resistance ratio or any PVT-independent reference voltages could also be set as a target voltage level.

Abstract: A circuit for recycling energy in bit lines (BL and BLB) of SRAM during write operation by (i) storing the charges BL and BLB to an intermediate voltage source (VLB) in a discharge phase and (ii) restoring the charges from the intermediate voltage, back to the BL or BLB in a recovery phase. The circuit includes an inductor, a pair of NMOS transistors, a series resonance node, and an energy source (VLB) in addition to the components of an SRAM input-output circuit shown as in FIG. 1. During the SRAM write operation, the BL or BLB is discharged to the energy source VLB through the pair of NMOS transistors and, the inductor and the series resonance node. The remaining energy in the BL and the BLB is discharged to ground using the write complementary write drivers.

Abstract: Described herein are reduced-power electronic circuits with wide-band energy recovery using non-interfering topologies. A resonant clock distribution network comprises a plurality of resonant clock drivers that receive at least one of a plurality of reference clock signals. An energy saving component is coupled with the plurality of resonant clock drivers. The energy saving component provides for lower energy consumption by resonating with unwanted parasitic capacitance of a load capacitance. The energy saving component and the load capacitance (LC) form a series resonant frequency that is significantly greater than a clock frequency of the plurality of resonant clock drivers, so that output clock signal paths are not interfered with and so that effects on skew are minimized.

Abstract: Reduced-power dynamic data circuits with wide-band energy recovery are described herein. In one embodiment, a circuit system comprises at least one sub-circuit in which at least one of the sub-circuits includes a capacitive output node that is driven between low and high states in a random manner for a time period and an inductive circuit path coupled to the capacitive output node. The inductive circuit path includes a transistor switch and an inductor connected in series to discharge and recharge the output node to a bias supply. A pulse generator circuit generates a pulse width that corresponds to a timing for driving the output node.

Abstract: Disclosed is a resonant circuit and method for matched clock and data timing performance for improving timing closure of digital circuits on advanced semiconductor manufacturing processes. The matched resonance circuit comprises pulse generator circuit (202) and plurality of generating latches (206A-N) and plurality of sampling latches (304A-N). The pulse generator circuit (202) comprises plurality of inverters (210A-N), optimum resistance (214) and exclusive OR (Ex-OR) gate (218) which are connected in series and a matched capacitance. The pulse generator circuit (202) generates timing pulse output using one or more buffers and clock inductor. Each generating latch receives clock timing pulse output as timing pulse into plurality of sampling flip-flop latches (304A-N) through clock sample path (CS) to match arrival of timing pulse and outputs of plurality of input data lines that are resonated by connecting one or more of respective load capacitances with at least one shared inductor (208).

Abstract: Reduced-power dynamic data circuits with wide-band energy recovery are described herein. In one embodiment, a circuit system comprises at least one sub-circuit in which at least one of the sub-circuits includes a capacitive output node that is driven between low and high states in a random manner for a time period and an inductive circuit path coupled to the capacitive output node. The inductive circuit path includes a transistor switch and an inductor connected in series to discharge and recharge the output node to a bias supply. A pulse generator circuit generates a pulse width that corresponds to a timing for driving the output node.

Abstract: Disclosed is an auto-calibration circuit and method to generate the precise pulses that are required for energy savings achieved by using wide-band resonating cells for digital circuits. The calibration circuit performs a calibration technique by programming the number of PMOS devices and NMOS devices in parallel to an inverter, and these numbers are dynamically changed based on a target reference voltage that is defined by a resistance ratio or any PVT-independent reference voltages could also be set as a target voltage level.

Abstract: Disclosed is a resonant circuit and method for matched clock and data timing performance for improving timing closure of digital circuits on advanced semiconductor manufacturing processes. The matched resonance circuit comprises pulse generator circuit (202) and plurality of generating latches (206A-N) and plurality of sampling latches (304A-N). The pulse generator circuit (202) comprises plurality of inverters (210A-N), optimum resistance (214) and exclusive OR (Ex-OR) gate (218) which are connected in series and a matched capacitance. The pulse generator circuit (202) generates timing pulse output using one or more buffers and clock inductor. Each generating latch receives clock timing pulse output as timing pulse into plurality of sampling flip-flop latches (304A-N) through clock sample path (CS) to match arrival of timing pulse and outputs of plurality of input data lines that are resonated by connecting one or more of respective load capacitances with at least one shared inductor (208).

Abstract: Described herein are reduced-power electronic circuits with wide-band energy recovery using non-interfering topologies. A resonant clock distribution network comprises a plurality of resonant clock drivers that receive at least one of a plurality of reference clock signals. An energy saving component is coupled with the plurality of resonant clock drivers. The energy saving component provides for lower energy consumption by resonating with unwanted parasitic capacitance of a load capacitance. The energy saving component and the load capacitance (LC) form a series resonant frequency that is significantly greater than a clock frequency of the plurality of resonant clock drivers, so that output clock signal paths are not interfered with and so that effects on skew are minimized.

Abstract: Described herein are reduced-power electronic circuits with wide-band energy recovery using non-interfering topologies. A resonant clock distribution network comprises a plurality of resonant clock drivers that receive at least one of a plurality of reference clock signals. An energy saving component is coupled with the plurality of resonant clock drivers. The energy saving component provides for lower energy consumption by resonating with unwanted parasitic capacitance of a load capacitance. The energy saving component and the load capacitance (LC) form a series resonant frequency that is significantly greater than a clock frequency of the plurality of resonant clock drivers, so that output clock signal paths are not interfered with and so that effects on skew are minimized.

Abstract: Described herein are reduced-power electronic circuits with wide-band energy recovery using non-interfering topologies. A digital logic driver comprising a pulldown switch, an energy saving component (e.g., inductor) coupled in series with the pulldown switch, and a reference supply connected in series with the energy saving component that is configured to enable the digital logic driver to resonate with a load capacitance and reuse electrical energy at the load capacitance without interfering with a signal path of the digital logic driver.

Abstract: Reduced-power dynamic data circuits with wide-band energy recovery are described herein. In one embodiment, a circuit system comprises at least one sub-circuit in which at least one of the sub-circuits includes a capacitive output node that is driven between low and high states in a random manner for a time period and an inductive circuit path coupled to the capacitive output node. The inductive circuit path includes a transistor switch and an inductor connected in series to discharge and recharge the output node to a bias supply. A pulse generator circuit generates a pulse width that corresponds to a timing for driving the output node.

Abstract: Described herein are reduced-power electronic circuits with wide-band energy recovery using non-interfering topologies. A resonant clock distribution network comprises a plurality of resonant clock drivers that receive at least one of a plurality of reference clock signals. An energy saving component is coupled with the plurality of resonant clock drivers. The energy saving component provides for lower energy consumption by resonating with unwanted parasitic capacitance of a load capacitance. The energy saving component and the load capacitance (LC) form a series resonant frequency that is significantly greater than a clock frequency of the plurality of resonant clock drivers, so that output clock signal paths are not interfered with and so that effects on skew are minimized.

Abstract: Described herein are reduced-power electronic circuits with wide-band energy recovery using non-interfering topologies. A digital logic driver comprising a pulldown switch, an energy saving component (e.g., inductor) coupled in series with the pulldown switch, and a reference supply connected in series with the energy saving component that is configured to enable the digital logic driver to resonate with a load capacitance and reuse electrical energy at the load capacitance without interfering with a signal path of the digital logic driver.

Abstract: A radio frequency synthesizer receives a relatively low frequency input signal and synthesizes from it a high frequency output signal whose frequency can be programmed to change in fine steps, for use e.g. in cordless telephone. The frequency synthesizer includes three linked phase locked loops with a single side band mixer in one embodiment coupling two of the phase locked loops together. This provides an output signal free of in-band frequency spurs within the spacing of two channels. The synthesizer can be integrated in a single chip with a narrowband FM modulation circuit. In spite of using a novel synthesizer to achieve monolithic integration, the user programming interface and control value equations are the industry standard format.

Abstract: A CMOS rail-to-rail input/output operational amplifier has constant supply current with respect to the input signal's common mode voltage. By use of current bleeders, i.e. a smaller transistor of opposite conductivity type connected in parallel with each transistor in the differential pair of transistors, there is provided constant transconductance and constant supply current for rail-to-rail operation with respect to the positive and negative supply voltages. This allows production of a low cost, high performance and small area rail-to-rail input/output operational amplifier.