Patents by Inventor Ignazio Urzi

Ignazio Urzi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8571016
    Abstract: A plurality of inputs are configured to receive circuit switched traffic from a plurality of initiators. A plurality of outputs are configured to output said traffic to a network on chip. Each output is associated with a different quality of service traffic. A traffic controller directs the received circuit switched traffic to respective ones of the outputs in dependence on a quality of service associated with the traffic.
    Type: Grant
    Filed: June 15, 2011
    Date of Patent: October 29, 2013
    Assignee: STMicroelectronics (R&D) Ltd
    Inventors: Ignazio Urzi, Daniele Mangano, Claire Bonnet
  • Publication number: 20120008620
    Abstract: A plurality of inputs are configured to receive circuit switched traffic from a plurality of initiators. A plurality of outputs are configured to output said traffic to a network on chip. Each output is associated with a different quality of service traffic. A traffic controller directs the received circuit switched traffic to respective ones of the outputs in dependence on a quality of service associated with the traffic.
    Type: Application
    Filed: June 15, 2011
    Publication date: January 12, 2012
    Applicant: STMICROELECTRONICS (R&D) LTD
    Inventors: Ignazio Urzi, Daniele Mangano, Claire Bonnet
  • Patent number: 7036038
    Abstract: A converter circuit for performing transfer of control logic signals between a first device and a second device in connection with an interconnection bus, the first device operating at the frequency of a first clock signal and the second device operating at the frequency of a second clock signal. The clock frequencies may be in a first ratio to one another corresponding to unity, as well as in a second and a third ratio. The converter circuit includes manipulation circuit elements which define respective propagation paths through the converter circuit for control signals. A logic network may assume three states, corresponding, respectively, to the first, second and third ratios between the frequencies of the clock signals, selectively interposing the manipulation elements in the propagation paths.
    Type: Grant
    Filed: March 20, 2003
    Date of Patent: April 25, 2006
    Assignee: STMicroelectronics, S.r.l.
    Inventors: Ignazio UrzĂ­, Massimiliano Fieni, Salvatore Pisasale
  • Publication number: 20030198287
    Abstract: A converter circuit for performing transfer of control logic signals between a first device and a second device in connection with an interconnection bus, the first device operating at the frequency of a first clock signal and the second device operating at the frequency of a second clock signal. The clock frequencies may be in a first ratio to one another corresponding to unity, as well as in a second and a third ratio. The converter circuit includes manipulation circuit elements which define respective propagation paths through the converter circuit for control signals. A logic network may assume three states, corresponding, respectively, to the first, second and third ratios between the frequencies of the clock signals, selectively interposing the manipulation elements in the propagation paths.
    Type: Application
    Filed: March 20, 2003
    Publication date: October 23, 2003
    Applicant: STMicroelectronics S.r.l.
    Inventors: Ignazio Urzi, Massimiliano Fieni, Salvatore Pisasale