Abstract: Bidirectional differential point to point simultaneous high speed signalling is provided between integrated circuits with highly effective echo canceling. Each integrated circuit comprises a transmitter for transmitting a first signal to another integrated circuit and a receiver for receiving a second signal from the other integrated circuit. The transmitter has an output buffer; a receiver has a receiver buffer and is co-located on the same integrated circuit; and a differential buffer is coupled between the input of the transmitter buffer and the output of the receiver buffer. To increase the quality of receiving the second signal, a third signal adjusted in phase and amplitude is coupled at the output of the receive buffer, so that the echoing of the first signal is canceled. Preferably, the rise time of the third signal is also adjusted.

Abstract: A reference voltage generator and a method for generating a reference voltage for a logic device using the reference voltage generator is provided. The voltage reference generator includes a ring oscillator having a plurality of logic gates and a phase/frequency detector. A first reference voltage is generated on the basis of a phase/frequency difference between the phase/frequency of a reference clock and the phase/frequency of the ring oscillator. A second reference voltage is generated on the basis of a voltage swing of the oscillator circuit. Both reference voltages can be applied to the plurality of logic gates of the ring oscillator such that a constant delay is created through each logic gate of the logic device.

Abstract: A timing delay generator for supplying a signal delayed by a predetermined period comprises a vernier that provides variable delays for a main signal, the delays being sensitive to temperature variation, a sensor for sensing the vernier's temperature and a feedback loop to maintain the temperature of the silicon die at a constant level and thus, to provide the high long-term accuracy of the timing delay generator.

Abstract: A data transmission apparatus and method employing the phase noise characteristics within the receiving registers to measure and control the characteristics of the channel as a function of the data pattern and to compensate for production tolerances within the channel by altering the timing characteristics of the signal at either the transmitter or receiver as a function of the data. Time offsets between different signals that form the communication channel are measured for different frequencies and/or for different data patterns transmitted through the channel and stored to compensate for an inter-signal skew by performing relative alignment of the measured offsets to a main clock edge.

Abstract: An amplifier circuit for receiving an input signal and providing an output signal, comprises a main chain of logic stages with a plurality of nodes therebetween, and at least one auxiliary chain nested between one node in the main chain and another node, which is not the next node, to form a series of feed back or feed forward nested equalisation loops; whereby the input signal is fed serially down the main chain and is also fed through the said at least one auxiliary chain and summed to provide the output signal. The invention overcomes gain-bandwidth limits of the drive stages and bandwidth reductions that occur when analogue stages operating in a linear mode are concatenated.

Abstract: The present invention relates to high speed communications, in particular, to an interface device between a transmitting device and a receiving device of a transmission system, wherein the transmitting device is capable of automatic compensation of cross-talk timing errors in the interface device, for a group of signals, by using information stored in a storage attached to that interface device. Preferably, the data stored in said storage comprises data on interconnections between said first and second plurality of terminals and data on crosstalk timing errors in said transmission lines relating to a specific data pattern, for each of said stored interconnection.

Abstract: A means for reducing the power consumption of the transmitter by storing the recent history of the transmitted data using a string of gates with taps from the string taken at points determined by the propagation delay of each gate and controlling driving transistors as a function of comparison of that history with input data so that, either the signal is driven into the transmission line at full strength, or at a level near the minimum needed to retain the state in the receiver. The advantage of the invention is that the line capacitance decays through the terminating resistors or discharge transistors, such that when the next state change is needed, then line has less stored energy needing to be discharged.

Abstract: The present invention relates to the reduction of artifacts introduced by sending data at a higher rate than the bandwidth of the communication channel, such as the voltage and current offsets introduced in the data at the receiver as a function of the preceding data.

Abstract: A timing control device and method for minimizing timing uncertainties due to skew and jitter, wherein a device for the compensation of timing errors in multiple channel electronic devices comprises at least one register having a plurality of channels comprising: a clock for providing a clock signal; a reference signal generator for generating reference signals for deskewing the registers. For each register, a corresponding feedback loop is associated for the relative alignment of the register's timing. The feedback loop comprises a device for detecting a deviation from a predetermined level of probability of reading by the register of a desired symbol on a boundary of two reference channel symbols in a sequence, and a set of delay devices which use the detected values of probability to generate a feedback signal.

Abstract: The present invention relates to a pull-up structure with variable strength, which combines a resistor network with N type MOS transistors. According to the invention, the pull up structure comprises an N-channel type MOSFET with a resistor in parallel. Alternatively, a resistor is connected between the terminal of the pull up and a voltage supply, or between the source of the N Type MOSFET and the terminal of the pull up, i.e. in series with the gate. This allows the pull up to be varied to compensate for process and temperature variations around a predefined pull-up strength, and at the same time provides low parasitic capacitance and a good dynamic response of the pull-up structure.

Abstract: The present invention relates to a coding apparatus for encoding data represented by 8 bit input symbols into 12 bit output codes for serially transmitting the codes along a communication channel, the codes being represented in the channel by signals having a limited minimum and maximum pulse width and sampled by a receiver at each receiver's clock period. The invention reduces artifacts introduced by sending data at a higher payload rate than the bandwidth of the communication channel, such as the voltage and current offsets introduced in the data at the receiver as a function of the preceding data.

Abstract: A means for reducing the power consumption of the transmitter by storing the recent history of the transmitted data using a string of gates with taps from the string taken at points determined by the propagation delay of each gate and controlling driving transistors as a function of comparison of that history with input data so that, either the signal is driven into the transmission line at full strength, or at a level near the minimum needed to retain the state in the receiver.

Abstract: Bidirectional differential point to point simultaneous high speed signalling is provided between integrated circuits with highly effective echo canceling. Each integrated circuit comprises a transmitter for transmitting a first signal to another integrated circuit and a receiver for receiving a second signal from the other integrated circuit. The transmitter has an output buffer; a receiver has a receiver buffer and is co-located on the same integrated circuit; and a differential buffer is coupled between the input of the transmitter buffer and the output of the receiver buffer. To increase the quality of receiving the second signal, a third signal adjusted in phase and amplitude is coupled at the output of the receive buffer, so that the echoing of the first signal is canceled. Preferably, the rise time of the third signal is also adjusted.

Abstract: Bidirectional differential point to point simultaneous high speed signalling is provided between integrated circuits with highly effective echo canceling. Each integrated circuit comprises a transmitter for transmitting a first signal to another integrated circuit and a receiver for receiving a second signal from the other integrated circuit. The transmitter has an output buffer; a receiver has a receiver buffer and is co-located on the same integrated circuit; and a differential buffer is coupled between the input of the transmitter buffer and the output of the receiver buffer. To increase the quality of receiving the second signal, a third signal adjusted in phase and amplitude is coupled at the output of the receive buffer, so that the echoing of the first signal is canceled.

Abstract: A transmission system and method for transmission of digital data with impedance matching at the terminal ends reduces reflected signals due to impedance mismatch at the terminating ends and due to impedance transition areas in the transmission line. The transmission system includes a transmission line having a driver end connected to a driving circuit and a receiving end connected to a receiving circuit, each said end having an adjustable termination means connected thereto On the driver end of the transmission line said adjustable termination means is incorporated in the driving circuit, while on the receiver end of the transmission line said adjustable termination means is connected in parallel with the receiving circuit. Thus, both the reflections produced on the ends of a transmission line and the reflections resulting from discontinuities within a transmission line will be terminated.

Abstract: A high precision receiver with a means to reduce or compensate the skew caused by the receiver's hysteresis by using a dynamic reference that is varied depending on a current output signal. To avoid oscillation, the reference signal can be switched over with a certain delay.

Abstract: A data transmission means and method employing the phase noise characteristics within the receiving registers to measure and control the characteristics of the channel as a function of the data pattern and to compensate for production tolerances within the channel by altering the timing characteristics of the signal at either the transmitter or receiver as a function of the data. Time offsets between different signals that form the communication channel are measured for different frequencies and/or for different data patterns transmitted through the channel and stored to compensate for an inter-signal skew by performing relative alignment of the measured offsets to a main clock edge.

Abstract: The present invention relates to systems for communicating with synchronous devices, in particular, to automatic test equipment (ATE) for memory device testing and, more specifically, to a test system for testing a high-speed synchronous memory device using DQS signals obtained from the memory device to achieve the precise fault strobe timing characteristics. The test system for testing a memory device comprises a synchronisation unit for triggering fault strobe generators with respect to DQS signals from the memory device under test. The invention is particularly appropriate for testing memory devices having reference signal for data receiver synchronisation, such as DDR Synchronous Dynamic Random Access Memory (DDR SDRAM), DDR SGRAM (Synchronous Graphics Random Access Memory), DDR II SDRAM, QDR SRAM, etc.

Abstract: A distributed terminator for terminating a transmission line linking a plurality of integrated circuits. The terminator comprises a plurality of resistors and a capacitor that is usually an ESD structure. The values of the resistors are such that the reflection co-efficient of the combined termination is lower across the bandwidth of the signal being transmitted than a reflection coefficient with a termination using resistors in the same topology where the effective value of the resistors is equal to the line impedance.

Abstract: The present invention relates to the reduction of artifacts introduced by sending data at a higher rate than the bandwidth of the communication channel, such as the voltage and current offsets introduced in the data at the receiver as a function of the preceding data.