Patents by Inventor Igor G. Kouznetsov
Igor G. Kouznetsov has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9627073Abstract: Systems, methods, and apparatus are disclosed for implementing memory cells having common source lines. The methods may include receiving a first voltage at a first transistor. The first transistor may be coupled to a second transistor and included in a first memory cell. The methods include receiving a second voltage at a third transistor. The third transistor may be coupled to a fourth transistor and included in a second memory cell. The first and second memory cells may be coupled to a common source line. The methods include receiving a third voltage at a gate of the second transistor and a gate of the fourth transistor that may cause them to operate in cutoff mode. The methods may include receiving a fourth voltage at a gate of the first transistor. The fourth voltage may cause a change in a charge storage layer included in the first transistor.Type: GrantFiled: September 20, 2016Date of Patent: April 18, 2017Assignee: CYPRESS SEMICONDUCTOR CORPORATIONInventors: Xiaojun Yu, Venkatraman Prabhakar, Igor G. Kouznetsov, Long Hinh, Bo Jin
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Patent number: 9620516Abstract: Memory devices and methods for forming the same are disclosed. In one embodiment, the device includes a non-volatile memory (NVM) transistor formed in a first region of a substrate, the NVM transistor comprising a channel and a gate stack on the substrate overlying the channel. The gate stack includes a dielectric layer on the substrate, a charge-trapping layer on the dielectric layer, an oxide layer overlying the charge-trapping layer, a first gate overlying the oxide layer, and a first silicide region overlying the first gate. The device includes a metal-oxide-semiconductor transistor formed in a second region of the substrate comprising a gate oxide overlying the substrate in the second region, a second gate overlying the gate oxide, and a second silicide region overlying the second gate. A strain inducing structure overlies at least the NVM transistor and a surface of the substrate in the first region of the substrate.Type: GrantFiled: May 4, 2016Date of Patent: April 11, 2017Assignee: Cypress Semiconductor CorporationInventors: Krishnaswamy Ramkumar, Igor G. Kouznetsov, Venkatraman Prabhakar
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Publication number: 20170053703Abstract: A method of erasing, during an erase operation, a non-volatile memory (NVM) cell of a memory device is disclosed. The erasing includes applying a first HV signal (VPOS) to a common source line (CSL). The CSL is shared among NVM cells of a sector of NVM cells. The first HV signal is above a highest voltage of a power supply. The erasing also includes applying the first HV signal to a local bit line (BL).Type: ApplicationFiled: September 18, 2015Publication date: February 23, 2017Inventors: Bogdan I. Georgescu, Gary P. Mosculak, Vijay Raghavan, Igor G. Kouznetsov
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Publication number: 20170011807Abstract: A non-volatile memory and methods of operating the same to reduce disturbs is provided. In one embodiment, the method includes coupling a first positive high voltage to a first global wordline in a first row of an array of memory cells, and coupling a second negative high voltage (VNEG) to a first bitline in a first column of the array to apply a bias to a non-volatile memory transistor in a selected memory cell to program the selected memory cell. A margin voltage having a magnitude less than VNEG is coupled to a second global wordline in a second row of the array, and an inhibit voltage coupled to a second bitline in a second column of the array to reduce a bias applied to a non-volatile memory transistor in an unselected memory cell to reduce program disturb of data programmed in the unselected memory cell due to programming.Type: ApplicationFiled: August 30, 2016Publication date: January 12, 2017Inventors: Ryan T. Hirose, Igor G. Kouznetsov, Venkatraman Prabhakar, Kaveh Shakeri, Bogdan Georgescu
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Publication number: 20170011800Abstract: Systems, methods, and apparatus are disclosed for implementing memory cells having common source lines. The methods may include receiving a first voltage at a first transistor. The first transistor may be coupled to a second transistor and included in a first memory cell. The methods include receiving a second voltage at a third transistor. The third transistor may be coupled to a fourth transistor and included in a second memory cell. The first and second memory cells may be coupled to a common source line. The methods include receiving a third voltage at a gate of the second transistor and a gate of the fourth transistor that may cause them to operate in cutoff mode. The methods may include receiving a fourth voltage at a gate of the first transistor. The fourth voltage may cause a change in a charge storage layer included in the first transistor.Type: ApplicationFiled: September 20, 2016Publication date: January 12, 2017Inventors: Xiaojun Yu, Venkatraman Prabhakar, Igor G. Kouznetsov, Long Hinh, Bo Jin
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Patent number: 9466374Abstract: Systems, methods, and apparatus are disclosed for implementing memory cells having common source lines. The methods may include receiving a first voltage at a first transistor. The first transistor may be coupled to a second transistor and included in a first memory cell. The methods include receiving a second voltage at a third transistor. The third transistor may be coupled to a fourth transistor and included in a second memory cell. The first and second memory cells may be coupled to a common source line. The methods include receiving a third voltage at a gate of the second transistor and a gate of the fourth transistor that may cause them to operate in cutoff mode. The methods may include receiving a fourth voltage at a gate of the first transistor. The fourth voltage may cause, via Fowler-Nordheim tunneling, a change in a charge storage layer included in the first transistor.Type: GrantFiled: February 10, 2015Date of Patent: October 11, 2016Assignee: Cypress Semiconductor CorporationInventors: Xiaojun Yu, Venkatraman Prabhakar, Igor G. Kouznetsov, Long T Hinh, Bo Jin
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Publication number: 20160260730Abstract: Memory devices and methods for forming the same are disclosed. In one embodiment, the device includes a non-volatile memory (NVM) transistor formed in a first region of a substrate, the NVM transistor comprising a channel and a gate stack on the substrate overlying the channel. The gate stack includes a dielectric layer on the substrate, a charge-trapping layer on the dielectric layer, an oxide layer overlying the charge-trapping layer, a first gate overlying the oxide layer, and a first silicide region overlying the first gate. The device includes a metal-oxide-semiconductor transistor formed in a second region of the substrate comprising a gate oxide overlying the substrate in the second region, a second gate overlying the gate oxide, and a second silicide region overlying the second gate. A strain inducing structure overlies at least the NVM transistor and a surface of the substrate in the first region of the substrate.Type: ApplicationFiled: May 4, 2016Publication date: September 8, 2016Inventors: Krishnaswamy Ramkumar, Igor G. Kouznetsov, Venkatraman Prabhakar
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Patent number: 9431124Abstract: A non-volatile memory and methods of operating the same to reduce disturbs is provided. In one embodiment, the method includes coupling a first positive high voltage to a first global wordline in a first row of an array of memory cells, and coupling a second negative high voltage (VNEG) to a first bitline in a first column of the array to apply a bias to a non-volatile memory transistor in a selected memory cell to program the selected memory cell. A margin voltage having a magnitude less than VNEG is coupled to a second global wordline in a second row of the array, and an inhibit voltage coupled to a second bitline in a second column of the array to reduce a bias applied to a non-volatile memory transistor in an unselected memory cell to reduce program disturb of data programmed in the unselected memory cell due to programming.Type: GrantFiled: March 20, 2015Date of Patent: August 30, 2016Assignee: Cypress Semiconductor CorporationInventors: Ryan T. Hirose, Igor G. Kouznetsov, Venkatraman Prabhakar, Kaveh Shakeri, Bogdan Georgescu
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Patent number: 9356035Abstract: A memory device that includes a non-volatile memory (NVM) transistor which has an indium doped channel and a gate stack overlying the channel formed in a first region of a substrate and a metal-oxide-semiconductor (MOS) transistor formed in a second region of the substrate in which the gate oxide of the MOS and the oxide layer of the NVM transistor are formed concurrently.Type: GrantFiled: August 4, 2014Date of Patent: May 31, 2016Assignee: Cypress Semiconductor CorporationInventors: Krishnaswamy Ramkumar, Igor G. Kouznetsov, Venkatraman Prabhakar
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Publication number: 20160005475Abstract: A system including a memory architecture is described. In one embodiment, the memory architecture includes an array of non-volatile memory cells, a first independently controlled voltage generation circuit, a plurality of register bits to store programmable values used by the independently controlled voltage generation circuit and a control circuit coupled to the first independently controlled voltage generation circuit. The first independently controlled voltage generation circuit is coupled to supply a positive voltage to the array during program and erase operations so that a magnitude of the positive voltage is applied across a storage note of an accessed memory cell of the array. The plurality of register bits to store programmable values used by the independently controlled voltage generation circuit to control the magnitude of the positive voltage. The control circuit controls a duration of the positive voltage. Other embodiments are also described.Type: ApplicationFiled: April 15, 2015Publication date: January 7, 2016Inventors: Ryan Tasuo Hirose, Fredrick B. Jenne, Vijay Raghavan, Igor G. Kouznetsov, Paul Fredrick Ruths, Cristinel Zonte, Bogdan I. Georgescu, Leonard Vasile Gitlan, James Paul Myers
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Patent number: 9171857Abstract: There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.Type: GrantFiled: September 23, 2014Date of Patent: October 27, 2015Assignee: SANDISK 3D LLCInventors: Thomas H. Lee, Vivek Subramanian, James M. Cleeves, Igor G. Kouznetsov, Mark G. Johnson, Paul Michael Farmwald
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Publication number: 20150294731Abstract: A non-volatile memory and methods of operating the same to reduce disturbs is provided. In one embodiment, the method includes coupling a first positive high voltage to a first global wordline in a first row of an array of memory cells, and coupling a second negative high voltage (VNEG) to a first bitline in a first column of the array to apply a bias to a non-volatile memory transistor in a selected memory cell to program the selected memory cell. A margin voltage having a magnitude less than VNEG is coupled to a second global wordline in a second row of the array, and an inhibit voltage coupled to a second bitline in a second column of the array to reduce a bias applied to a non-volatile memory transistor in an unselected memory cell to reduce program disturb of data programmed in the unselected memory cell due to programming.Type: ApplicationFiled: March 20, 2015Publication date: October 15, 2015Inventors: Ryan T. Hirose, Igor G. Kouznetsov, Venkatraman Prabhakar, Kaveh Shakeri, Bogdan Georgescu
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Publication number: 20150287464Abstract: Systems, methods, and apparatus are disclosed for implementing memory cells having common source lines. The methods may include receiving a first voltage at a first transistor. The first transistor may be coupled to a second transistor and included in a first memory cell. The methods include receiving a second voltage at a third transistor. The third transistor may be coupled to a fourth transistor and included in a second memory cell. The first and second memory cells may be coupled to a common source line. The methods include receiving a third voltage at a gate of the second transistor and a gate of the fourth transistor that may cause them to operate in cutoff mode. The methods may include receiving a fourth voltage at a gate of the first transistor. The fourth voltage may cause, via Fowler-Nordheim tunneling, a change in a charge storage layer included in the first transistor.Type: ApplicationFiled: February 10, 2015Publication date: October 8, 2015Inventors: Xiaojun Yu, Venkatraman Prabhakar, Igor G. Kouznetsov, Long T Hinh, Bo Jin
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Patent number: 8988938Abstract: A non-volatile memory and methods of operating the same to reduce disturbs is provided. In one embodiment, the method includes coupling a first positive high voltage to a first global wordline in a first row of an array of memory cells, and coupling a second negative high voltage (VNEG) to a first bitline in a first column of the array to apply a bias to a non-volatile memory transistor in a selected memory cell to program the selected memory cell. A margin voltage having a magnitude less than VNEG is coupled to a second global wordline in a second row of the array, and an inhibit voltage coupled to a second bitline in a second column of the array to reduce a bias applied to a non-volatile memory transistor in an unselected memory cell to reduce program disturb of data programmed in the unselected memory cell due to programming.Type: GrantFiled: March 17, 2014Date of Patent: March 24, 2015Assignee: Cypress Semiconductor CorporationInventors: Ryan T. Hirose, Igor G. Kouznetsov, Venkatraman Prabhakar, Kaveh Shakeri, Bogdan I. Georgescu
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Publication number: 20150041881Abstract: A memory device that includes a non-volatile memory (NVM) transistor which has an indium doped channel and a gate stack overlying the channel formed in a first region of a substrate and a metal-oxide-semiconductor (MOS) transistor formed in a second region of the substrate in which the gate oxide of the MOS and the oxide layer of the NVM transistor are formed concurrently.Type: ApplicationFiled: August 4, 2014Publication date: February 12, 2015Inventors: Krishnaswamy Ramkumar, Igor G. Kouznetsov, Venkatraman Prabhakar
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Publication number: 20150044833Abstract: There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.Type: ApplicationFiled: September 23, 2014Publication date: February 12, 2015Inventors: Thomas H. Lee, Vivek Subramanian, James M. Cleeves, Igor G. Kouznetsov, Mark G. Johnson, Paul Michael Farmwald
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Publication number: 20140301139Abstract: A non-volatile memory and methods of operating the same to reduce disturbs is provided. In one embodiment, the method includes coupling a first positive high voltage to a first global wordline in a first row of an array of memory cells, and coupling a second negative high voltage (VNEG) to a first bitline in a first column of the array to apply a bias to a non-volatile memory transistor in a selected memory cell to program the selected memory cell. A margin voltage having a magnitude less than VNEG is coupled to a second global wordline in a second row of the array, and an inhibit voltage coupled to a second bitline in a second column of the array to reduce a bias applied to a non-volatile memory transistor in an unselected memory cell to reduce program disturb of data programmed in the unselected memory cell due to programming.Type: ApplicationFiled: March 17, 2014Publication date: October 9, 2014Applicant: CYPRESS SEMICONDUCTOR CORPORATIONInventors: Ryan T. Hirose, Igor G. Kouznetsov, Venkatraman Prabhakar, Kaveh Shakeri, Bogdan I. Georgescu
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Patent number: 8853765Abstract: There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.Type: GrantFiled: March 27, 2014Date of Patent: October 7, 2014Assignee: Sandisk 3D LLCInventors: Thomas H. Lee, Vivek Subramanian, James M. Cleeves, Igor G. Kouznetsov, Mark G. Johnson, Paul Michael Farmwald
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Publication number: 20140239374Abstract: Memory cells including embedded SONOS based non-volatile memory (NVM) and MOS transistors and methods of forming the same are described. Generally, the method includes: forming a dielectric stack on a substrate, the dielectric stack including a tunneling dielectric on the substrate and a charge-trapping layer on the tunneling dielectric; patterning the dielectric stack to form a gate stack of a NVM transistor of a memory device in a first region of the substrate while concurrently removing the dielectric stack from a second region of the substrate; and performing a gate oxidation process of a baseline CMOS process flow to thermally grow a gate oxide of a MOS transistor overlying the substrate in the second region while concurrently growing a blocking oxide overlying the charge-trapping layer. In one embodiment, Indium is implanted to form a channel of the NVM transistor.Type: ApplicationFiled: September 4, 2013Publication date: August 28, 2014Applicant: Cypress Semiconductor CorporationInventors: Krishnaswamy Ramkumar, Igor G. Kouznetsov, Venkatraman Prabhakar
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Publication number: 20140225180Abstract: There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.Type: ApplicationFiled: March 27, 2014Publication date: August 14, 2014Applicant: SANDISK 3D LLCInventors: Thomas H. Lee, Vivek Subramanian, James M. Cleeves, Igor G. Kouznetsov, Mark G. Johnson, Paul Michael Farmwald