Patents by Inventor Ihar Kasko
Ihar Kasko has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7442624Abstract: A method of forming alignment marks on edge chips in a kerf region of a semiconductor workpiece. The alignment marks are formed in at least one material layer of the semiconductor device. The alignment marks are formed using a separate lithography mask, and may extend into lower layers, including the workpiece, of the semiconductor device. An opaque material layer is deposited, and depressions are formed in the opaque layer over the deep alignment mark trenches. The depressions in the opaque material layer are used to align a lithography process to open the opaque material layer over alignment marks in an underlying metallization layer. The alignment marks in the metallization layer are then used to align the lithography process used to pattern the opaque material layer.Type: GrantFiled: August 2, 2004Date of Patent: October 28, 2008Assignee: Infineon Technologies AGInventors: Chandrasekhar Sarma, Ihar Kasko
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Patent number: 7374952Abstract: Methods of patterning a magnetic stack of a magnetic memory cell and structures thereof. At least the top magnetic material layer of a magnetic stack is patterned using a hard mask, and a conformal insulating material is deposited over the patterned top magnetic material layer and hard mask. The conformal insulating material is anisotropically etched to remove the conformal insulating material over vertical sidewalls of at least the patterned top magnetic material layer and the hard mask. The remaining conformal insulating material comprises a sidewall spacer hard mask that is used as a mask to pattern the remaining material layers of the magnetic stack. The sidewall spacer hard mask may be left remaining in the magnetic memory cell structure.Type: GrantFiled: June 17, 2004Date of Patent: May 20, 2008Assignees: Infineon Technologies AG, International Business Machines CorporationInventors: Ihar Kasko, Sivananda K. Kanakasabapathy, Gregory Costrini
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Patent number: 7272028Abstract: A magnetoresistive memory cell includes N magnetoresistive elements conductively connected in series (where N is an integer greater than or equal to two). The magnetoresistive elements, respectively, are positioned between at least two adjacent conductive lines. At least one of the conductive lines is a partially split conductive line having at least one slit portion encompassing an interconnect running therethrough and connected to at least one adjacent magnetoresistive element.Type: GrantFiled: May 27, 2005Date of Patent: September 18, 2007Assignees: Infineon Technologies AG, Altis Semiconductor SNCInventor: Ihar Kasko
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Publication number: 20060268600Abstract: A magnetoresistive memory cell includes N magnetoresistive elements conductively connected in series (where N is an integer greater than or equal to two). The magnetoresistive elements, respectively, are positioned between at least two adjacent conductive lines. At least one of the conductive lines is a partially split conductive line having at least one slit portion encompassing an interconnect running therethrough and connected to at least one adjacent magnetoresistive element.Type: ApplicationFiled: May 27, 2005Publication date: November 30, 2006Inventor: Ihar Kasko
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Patent number: 7087438Abstract: The invention relates to a method of encapsulating conductive lines of semiconductor devices and a structure thereof. An encapsulating protective material, such as TaN, Ta, Ti, TiN, or combinations thereof is disposed over conductive lines of a semiconductor device. The encapsulating protective material protects the conductive lines from harsh etch chemistries when a subsequently deposited material layer is patterned and etched. The encapsulating protective material is conductive and may be left remaining in the completed semiconductor device. The encapsulating material is patterned using a masking material, and processing of the semiconductor device is then continued. The masking material may be left remaining in the structure as part of a subsequently deposited insulating material layer.Type: GrantFiled: July 26, 2004Date of Patent: August 8, 2006Assignees: Infineon Technologies AG, International Business Machines CorporationInventors: Ihar Kasko, Kia-Seng Low, John P. Hummel
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Publication number: 20060024923Abstract: A method of forming alignment marks on edge chips in a kerf region of a semiconductor workpiece. The alignment marks are formed in at least one material layer of the semiconductor device. The alignment marks are formed using a separate lithography mask, and may extend into lower layers, including the workpiece, of the semiconductor device. An opaque material layer is deposited, and depressions are formed in the opaque layer over the deep alignment mark trenches. The depressions in the opaque material layer are used to align a lithography process to open the opaque material layer over alignment marks in an underlying metallization layer. The alignment marks in the metallization layer are then used to align the lithography process used to pattern the opaque material layer.Type: ApplicationFiled: August 2, 2004Publication date: February 2, 2006Inventors: Chandrasekhar Sarma, Ihar Kasko
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Publication number: 20060019431Abstract: A method of encapsulating conductive lines of semiconductor devices and a structure thereof. An encapsulating protective material comprising TaN, Ta, Ti, TiN, or combinations thereof is disposed over conductive lines of a semiconductor device. The encapsulating protective material protects the conductive lines from harsh etch chemistries when a subsequently deposited material layer is patterned and etched. The encapsulating protective material is conductive and may be left remaining in the completed semiconductor device. The encapsulating material is patterned using a masking material, and processing of the semiconductor device is then continued. The masking material may be left remaining in the structure as part of a subsequently deposited insulating material layer.Type: ApplicationFiled: July 26, 2004Publication date: January 26, 2006Inventors: Ihar Kasko, Kia-Seng Low, John Hummel
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Patent number: 6984529Abstract: A method of fabricating a magnetic tunnel junction (MTJ) device is provided. A patterned hard mask is oxidized to form a surface oxide thereon. An MTJ stack is etched in alignment with the patterned hard mask after the oxidizing of the patterned hard mask. Preferably, the MTJ stack etch recipe includes chlorine and oxygen. Etch selectivity between the hard mask and the MTJ stack is improved.Type: GrantFiled: September 10, 2003Date of Patent: January 10, 2006Assignees: Infineon Technologies AG, International Business Machines CorporationInventors: George Stojakovic, Rajiv M. Ranade, Ihar Kasko, Joachim Neutzel, Keith R. Milkove, Russell D. Allen, Kim Poong Mee Lee, legal representative, Young Hoon Lee, deceased
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Publication number: 20050280040Abstract: Methods of patterning a magnetic stack of a magnetic memory cell and structures thereof. At least the top magnetic material layer of a magnetic stack is patterned using a hard mask, and a conformal insulating material is deposited over the patterned top magnetic material layer and hard mask. The conformal insulating material is anisotropically etched to remove the conformal insulating material from horizontal surfaces of the device, leaving portions of the conformal insulating material over vertical sidewalls of at least the patterned top magnetic material layer and the hard mask. The remaining conformal insulating material comprises a sidewall spacer hard mask that is used as a mask to pattern the remaining material layers of the magnetic stack. The sidewall spacer hard mask may be left remaining in the magnetic memory cell structure.Type: ApplicationFiled: June 17, 2004Publication date: December 22, 2005Inventors: Ihar Kasko, Sivanandha Kanakasabapathy, Gregory Costrini
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Patent number: 6933204Abstract: A method for aligning an opaque, active device in a semiconductor structure includes forming an opaque layer over an optically transparent layer formed on a lower metallization level, the lower metallization level including one or more alignment marks formed therein. A portion of the opaque layer is patterned and opened corresponding to the location of the one or more alignment marks in the lower metallization level so as to render the one or more alignment marks optically visible. The opaque layer is then patterned with respect to the lower metallization level, using the optically visible one or more alignment marks.Type: GrantFiled: October 13, 2003Date of Patent: August 23, 2005Assignee: International Business Machines CorporationInventors: Chandrasekhar Sarma, Sivananda K. Kanakasabapathy, Ihar Kasko, Greg Costrini, John P. Hummel, Michael C. Gaidis
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Publication number: 20050079683Abstract: A method for aligning an opaque, active device in a semiconductor structure includes forming an opaque layer over an optically transparent layer formed on a lower metallization level, the lower metallization level including one or more alignment marks formed therein. A portion of the opaque layer is patterned and opened corresponding to the location of the one or more alignment marks in the lower metallization level so as to render the one or more alignment marks optically visible. The opaque layer is then patterned with respect to the lower metallization level, using the optically visible one or more alignment marks.Type: ApplicationFiled: October 13, 2003Publication date: April 14, 2005Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, INFINEON TECHNOLOGIES NORTH AMERICA CORP.Inventors: Chandrasekhar Sarma, Sivananda Kanakasabapathy, Ihar Kasko, Greg Costrini, John Hummel, Michael Gaidis
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Publication number: 20050051820Abstract: A method of fabricating a magnetic tunnel junction (MTJ) device is provided. A patterned hard mask is oxidized to form a surface oxide thereon. An MTJ stack is etched in alignment with the patterned hard mask after the oxidizing of the patterned hard mask. Preferably, the MTJ stack etch recipe includes chlorine and oxygen. Etch selectivity between the hard mask and the MTJ stack is improved.Type: ApplicationFiled: September 10, 2003Publication date: March 10, 2005Inventors: George Stojakovic, Rajiv Ranade, Ihar Kasko, Joachim Nuetzel, Keith Milkove, Russell Allen, Young Lee, Kim Lee
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Publication number: 20040229430Abstract: A magnetic random access memory device having a magnetic tunnel junction is provided, as well as methods of fabricating the same. The magnetic tunnel junction includes a first magnetic layer, a second magnetic layer, a tunnel barrier layer, and dielectric material portions. The first magnetic layer is formed over the second magnetic layer. The tunnel barrier layer is located between the first and second magnetic layers. The dielectric material portions are formed on sidewalls of the first magnetic layer and over the second magnetic layer. The dielectric material portions may be formed directly atop the second magnetic layer. In another embodiment, the dielectric material portion may be formed directly atop the tunnel barrier layer. Preferably, the dielectric material portions prevent shorts from developing across the tunnel barrier layer during the etching of the second magnetic layer.Type: ApplicationFiled: May 14, 2003Publication date: November 18, 2004Inventors: Frank Findeis, Ihar Kasko, Wolfgang Raberg
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Patent number: 6613640Abstract: The integrated ferroelectric semiconductor memory is fabricated according to the stack cell principle. A ferroelectric capacitor module is formed on an intermediate oxide above a selection transistor located in or on a semiconductor wafer. The capacitor module is brought into conductive contact by its bottom capacitor electrode with an electrode of the selection transistor by means of an electrically conductive plug leading through the intermediate oxide. A layer system of a conductive oxygen diffusion barrier and a conductive adhesion layer is deposited directly below the bottom capacitor electrode, and the adhesion layer and the overlying oxygen diffusion barrier are deposited directly into the contact hole and form the plug at least in the region lying directly below the bottom capacitor electrode.Type: GrantFiled: March 14, 2002Date of Patent: September 2, 2003Assignee: Infineon Technologies AGInventors: Ihar Kasko, Volker Weinrich, Matthias Krönke
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Publication number: 20020137301Abstract: The integrated ferroelectric semiconductor memory is fabricated according to the stack cell principle. A ferroelectric capacitor module is formed on an intermediate oxide above a selection transistor located in or on a semiconductor wafer. The capacitor module is brought into conductive contact by its bottom capacitor electrode with an electrode of the selection transistor by means of an electrically conductive plug leading through the intermediate oxide. A layer system of a conductive oxygen diffusion barrier and a conductive adhesion layer is deposited directly below the bottom capacitor electrode, and the adhesion layer and the overlying oxygen diffusion barrier are deposited directly into the contact hole and form the plug at least in the region lying directly below the bottom capacitor electrode.Type: ApplicationFiled: March 14, 2002Publication date: September 26, 2002Inventors: Ihar Kasko, Volker Weinrich, Matthias Kronke