Abstract: A timing error removing method includes selecting a logic-level correction location and a first buffer to be inserted at the logic-level correction location, wherein the logic-level correction location and the first buffer are able to remove a timing error in a semiconductor integrated circuit to be designed; and searching for a vacant area in the semiconductor integrated circuit where the first buffer can be placed for the logic-level correction location, and if the vacant area is not found, further searching for a combination of a plurality of buffers smaller than the first buffer, the combination of the plurality of buffers being able to be placed in the semiconductor integrated circuit and being able to replace the first buffer in terms of a delay obtained as if the first buffer is inserted.

Abstract: A timing error removing method includes selecting a logic-level correction location and a first buffer to be inserted at the correction location, the logic-level correction location and the first buffer being able to remove a timing error in a semiconductor integrated circuit to be designed; and searching for a vacant area in the semiconductor integrated circuit where the first buffer can be placed for the correction location, and if the vacant area is not found, further searching for a combination of a plurality of buffers smaller than the first buffer, the combination of the plurality of buffers being to be placed in the semiconductor integrated circuit and being able to replace the first buffer in terms of a delay obtained as if the first buffer is inserted.

Abstract: An arranging unit arranges a cell obtained from a net list input by an input unit on a large scale integration chip. A net extracting unit extracts an arbitrary net to be tested from a set of the cells arranged. An information extracting unit extracts, based on correlation information between information on a driving capacity of each of cells included in a circuit created based on a delay time caused by a crosstalk occurred as a result of a circuit simulation for a predetermined circuit model and information on a length of a wiring that connects the cells, wire-length information that has a correlation with information on the driving capacity of the cell in the net. An inserting unit inserts, based on the wire-length information, a delay-time suppressing cell to suppress a delay time in the net.

Abstract: A layout editor apparatus draws line segments constituting a first interconnect line connecting between an output pin and a first input pin so as to draw the first interconnect line as a straight line formed of the line segments connected in a line extending from the output pin only in a first direction, and draws line segments constituting a second interconnect line connecting between a branch point and a second input pin so as to draw the second interconnect line as a straight line formed of the line segments connected in a line extending only in the first direction from a point that is displaced from the branch point on the first interconnect line in a second direction perpendicular to the first direction, wherein the displayed lengths of the line segments are proportional to their physical lengths, and the displayed widths of the line segments reflect their physical widths.

Abstract: A layout editor apparatus draws line segments constituting a first interconnect line connecting between an output pin and a first input pin so as to draw the first interconnect line as a straight line formed of the line segments connected in a line extending from the output pin only in a first direction, and draws line segments constituting a second interconnect line connecting between a branch point and a second input pin so as to draw the second interconnect line as a straight line formed of the line segments connected in a line extending only in the first direction from a point that is displaced from the branch point on the first interconnect line in a second direction perpendicular to the first direction, wherein the displayed lengths of the line segments are proportional to their physical lengths, and the displayed widths of the line segments reflect their physical widths.

Abstract: An arranging unit arranges a cell obtained from a net list input by an input unit on a large scale integration chip. A net extracting unit extracts an arbitrary net to be tested from a set of the cells arranged. An information extracting unit extracts, based on correlation information between information on a driving capacity of each of cells included in a circuit created based on a delay time caused by a crosstalk occurred as a result of a circuit simulation for a predetermined circuit model and information on a length of a wiring that connects the cells, wire-length information that has a correlation with information on the driving capacity of the cell in the net. An inserting unit inserts, based on the wire-length information, a delay-time suppressing cell to suppress a delay time in the net.

Abstract: The invention provides a floor planning technique by which physical blocks having areas sufficiently matching with actual sub circuits can be produced automatically and also a physical block of a shape other than a rectangle can be produced using a very simple technique.