Abstract: A microprocessor comprising a bus state controller and for use in a personal computer or the like. The bus state controller includes control registers such as wait controllers, and in parallel controls the interfaces of various semiconductor memories (ROM, burst ROM, SRAM, PSRAM, DRAM and synchronous RAM) and PC cards (memory and I/O cards). Also included in the bus state controller is a control register for controlling the time to set up PC card start signals where a synchronous DRAM(s) is configured. The address space of an external bus of the microprocessor is divided into a predetermined number of areas to which the semiconductor memories and PC cards are fixedly assigned. The microprocessor further comprises a memory management unit for converting an internally prepared logical address to a physical address.

Abstract: A data processor supporting associative writing and comprising an associative memory and a central processing unit, the associative memory being furnished in the address space managed by the central processing unit. Any of the entries in the memory is accessed when the address of the entry in question in the address space is designated. With associative writing supported, data is allowed to be written to the designated address if the searched address information retained in the entry at the designated address matches the corresponding information held in the write data upon comparison. The write data is inhibited from being written to the designated address in case of a mismatch between the two kinds of information.

Abstract: A data processor for executing instructions using operand data stored in a main memory includes an instruction control unit having a first associative memory storing instructions read out from the main memory. The data processor also includes an instruction controller reading out an instruction from the first associative memory when the instructioon is present in the first associative memory and reading an instruction from the main memory when the instruction is not present in the first associative memory. The controller also has as an output the instruction to be executed. An instruction execution unit has a second associative memory storing operand data read out from the main memory. An instruction executioner executes the instruction by using operand data read out from the second associative memory when the operand data is present in the second associative memory and from the main memory when the operand data is not present in the second associative memory.

Abstract: A data processor capable of supporting a plurality of page sizes without increasing the chip occupation area or the power consumption. This data processor for supporting a virtual memory is constructed of a set associative type cache memory having a plurality of banks having their index addresses shared, in which the virtual page size can be set for each page and which includes a TLB to be shared among the plural virtual pages set in various manners. This TLB is provided with a latch field for latching a pair of the virtual page number and the physical page number. The maximum size of the virtual page to be supported is set to the power of two of the minimum size, and the bank number of the TLB is set to no less than the power of two of the former.

Abstract: A microcomputer has a clock generator capable of changing the frequency of an output clock signal: and a power circuit capable of changing the level of an operating voltage to be outputted. The frequencies of clock signals and the levels of operating voltages to be individually fed to a plurality of circuit modules can be dynamically changed according to the content of a packaged register. If the content of the register instructs the reduction of the clock signal frequency and the operating voltage in its absolute value, the operating voltage is lowered in its absolute value prior to the change in the clock signal frequency. On the contrary, if the instruction is to increase the frequency of the clock signal and the operating voltage in its absolute value, the clock signal having the increased frequency is outputted prior to the increase of the operating voltage in the absolute value.

Abstract: A microprocessor incorporating a PLL circuit using a clock pulse having a relatively low frequency as an input clock signal of a reference frequency to form an oscillating pulse of a relatively high frequency by multiplying the input clock signal. In the microprocessor, the operation of the PLL circuit is stopped in the low-speed mode to supply the clock pulse of the relatively low frequency to the microprocessor as a system clock signal, and, in the high-speed mode, the PLL circuit is activated upon reception of an event requiring high-speed processing. Until the operation of the PLL circuit is stabilized and the request for high-speed processing comes, the above-mentioned clock pulse having the relatively low frequency is kept supplied continuously to the microprocessor as the system clock signal. This novel setup permits the high-speed switching of the microprocessor from the operating mode to the high-speed operating mode.

Abstract: A data processor for executing instructions using operand data stored in a main memory includes an instruction control unit having a first associative memory storing instructions read out from the main memory. The data processor also includes an instruction controller reading out an instruction from the first associative memory when the instruction is present in the first associative memory and reading an instruction from the main memory when the instruction is not present in the first associative memory. The controller also has as an output; and an instruction execution unit has a second associative memory storing operand data read out from the main memory. An instruction executioner executes the instruction by using operand data read out from the second associative memory when the operand data is present in the second associative memory and from the main memory when the operand data is not present in the second associative memory.

Abstract: A microprocessor having a buffer or memory capable of holding a plurality of instructions in advance of execution also functions to insert a special bus cycle amongst the instructions for outputting the internal information of the microprocessor to the outside in a predetermined operation mode at the time of each execution. The information inside of the microprocessor, which is to be outputted to the outside in the special bus cycle, is identified by the address of the executed instruction in a memory space, an instruction code or the code for identifying said executed instruction in the instruction group prefetched. In an emulation of the system using the instruction prefetch type microprocessor, as described above, what instruction has been executed can be easily known from the outside to effect an accurate emulation analysis and to facilitate the analysis of trace data thereby to improve debugging efficiency.

Abstract: A microprocessor including instruction decoding apparatus, instruction execution apparatus and information holding apparatus. The microprocessor performs a first step of storing information specifying the kind of operation to be performed by the instruction execution apparatus, upon execution of a first instruction, in the information holding apparatus and a second step of causing the instruction execution apparatus to perform the kind of operation specified by information stored in the information holding apparatus when a second instruction is decoded and includes information specifying that the operation to be performed by the instruction execution apparatus is the kind of operation specified by the information stored in the information holding apparatus.

Abstract: A data processor is used with a main memory that stores operand data and instructions. The data processor itself includes two cache memories, one of which stores logical instruction addresses and corresponding instructions while the other stores logical operand addresses and corresponding operand data. A selector chooses whether a logical operand address or logical instruction address should access the respective cache memory or the main memory to obtain an instruction or operand data. Furthermore, the processor includes the capability of invalidating all of the data in either the instruction cache memory or operand cache memory based on a software instruction signal received at a purge unit.

Abstract: The microprocessor has an address converting buffer to convert logical addresses into physical addresses and a signal generator representing the timing for the microprocessor to retrieve conversion information from an external memory and write it into the address converting buffer. With this configuration, it is possible to determine the logical address from the physical address that was output to an external circuit, without the microprocessor outputting the logical address directly to the external circuit.

Abstract: An instruction execution unit of a microprocessor has an ALU, a barrel shifter and a plurality of registers and these circuit blocks are coupled to an internal bus. In response to a specific instruction, the microprocessor operated to transfer output data of the plurality of circuit blocks at a time, so that logical operation of the plurality of output data is carried out on the internal bus at a high speed. The specific instruction designates which ones of the plurality of circuit blocks should transfer data to the internal bus and which one of the plurality of circuit blocks should be stored with the results of the logical operation carried out on the internal bus.

Abstract: In addition to an ordinary bit field instruction without limitation which makes use of an offset value and a field width, a bit field instruction with limitation which does not calculate the spread of the bit field is separately installed. In the present invention the calculation for determination of the spread of the bit field is not performed when the bit field instruction with limitation is executed. In addition, when executing a bit field instruction with limitation, the offset value and the field width can be obtained directly as immediate values thereby decreasing the execution time of the instruction.

Abstract: A data processor for executing instructions using operand data stored in a main memory includes an instruction control unit having a first associative memory storing instructions read out from the main memory, and an instruction controller reading out an instruction from the first associative memory when the instruction is present in the first associative memory and from the main memory when the instruction is not present in the first associative memory the instruction control unit produces an output to be executed. An instruction execution unit has a second associative memory that stores operand data read out from the main memory, and an instruction executioner executing the instruction by using operand data read out from the second associative memory when the operand data is present in the second associative memory and from the main memory when the operand data is not present in the second associative memory.

Abstract: When a coprocessor communicates a plurality of data items with a master processor and a memory according to a bus access cycle activated by the master processor, the coprocessor is supplied therein with information indicating a data storage position as a data transfer source or destination. The master processor and coprocessor independently monitor the number of the sequence of data transfers or the end of the sequence of data transfer operations. As a consequence, when executing a sequence of plural data transfer operations, the coprocessor need not receive a command from the master processor for each data transfer thereto. Further, it is not required for the coprocessor to indicate the end of the sequence of data transfer cycles to the master processor since the master processor can determine this on its own.

Abstract: An instruction is constituted by a plurality of words, minimum necessary information necessary for effective address calculation of an operand is stored in a leading word and a word or words containing an operation specification field (operation words) are arranged to continue the first word. According to this system, the operation word can be decoded concurrently with the address calculation of the operand or the operand fetch operation. Therefore, there is no need to secure a time exclusively for decoding the operation word and the execution speed of the instruction requiring the operand can be improved.

Abstract: A method for searching the memory of a data processing apparatus including a decoder for decoding the contents of an instruction and an execution unit for executing is performed in response to an instruction based on an output from the decoder, the search instruction which identifies a desired data storage area from a plurality of data storage areas in the memory which includes an array data structure.

Abstract: A data processor for executing instructions using operand data stored in a main memory includes an instruction control unit having a first associative memory storing instructions read out from the main memory, and the instruction control unit also includes an instruction controller reading out an instruction from the first associative memory when the instruction is present in the first associative memory and from the main memory when the instruction is not present in the first associative memory. The instruction controller provides the instruction to be executed as an output. The data processor further includes an instruction execution unit having a second associative memory storing operand data read out from the main memory, and an instruction execution unit that executes the instruction.

Abstract: A microcomputer system has a microprocessor and a number of independent coprocessors for executing individual instructions according to instruction data sent from the microprocessor. An address bus and a data bus interconnect the coprocessors with the microprocessor. The microprocessor sends instruction data to the coprocessors via the data bus and concurrently sends coprocessor designation data to the coprocessors via the address bus. The coprocessor designated by the designation data reads and reacts to the instruction data while the other coprocessors within the system disregard the instruction data.

Abstract: A method for searching the memory of a data processing apparatus including a decoder for decoding the contents of an instruction and an execution unit for executing the instruction based on an output from the decoder is performed in response to a search instruction which identifies a desired data storage area from a plurality of data storage areas in the memory which includes an array data structure.