Abstract: An equalizer for equalizing an input data signal of a digital transmission filter for jitter, overshoot and undershoot in amplitude includes a delay circuit which delays an input non-return-to-zero (NRZ) data signal a specified number of bits by synchronizing the input data signal with a basic clock signal, and outputs a plurality of delayed data bit streams each corresponding to a respective delay element of the delay circuit. The delayed data bit streams are input to a logic circuit which produces a plurality of voltage control signals corresponding to patterns of logic symbols in the data bit streams of the delayed input data signal, these voltage control signals designating information as to how much the delayed input data signal will be distorted due to data signals adjacent thereto upon passing through a digital transmission filter.