Patents by Inventor Il Kwan Lee
Il Kwan Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10680097Abstract: A semiconductor device, comprising: a substrate; an active gate trench in the substrate; a source polysilicon pickup trench in the substrate; a polysilicon electrode disposed in the source polysilicon pickup trench; a gate pickup trench in the substrate; a first conductive region and a second conductive region disposed in the gate pickup trench, the first conductive region and the second conductive region being separated by oxide, wherein at least a portion of the oxide surrounding the first conductive region in the gate pickup trench is thicker than at least a portion of the oxide under the second conductive region; and a body region in the substrate.Type: GrantFiled: September 8, 2017Date of Patent: June 9, 2020Assignee: Alpha and Omega Semiconductor IncorporatedInventors: John Chen, Il Kwan Lee, Hong Chang, Wenjun Li, Anup Bhalla, Hamza Yilmaz
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Publication number: 20170373186Abstract: A semiconductor device, comprising: a substrate; an active gate trench in the substrate; a source polysilicon pickup trench in the substrate; a polysilicon electrode disposed in the source polysilicon pickup trench; a gate pickup trench in the substrate; a first conductive region and a second conductive region disposed in the gate pickup trench, the first conductive region and the second conductive region being separated by oxide, wherein at least a portion of the oxide surrounding the first conductive region in the gate pickup trench is thicker than at least a portion of the oxide under the second conductive region; and a body region in the substrate.Type: ApplicationFiled: September 8, 2017Publication date: December 28, 2017Inventors: John Chen, Il Kwan Lee, Hong Chang, Wenjun Li, Anup Bhalla, Hamza Yilmaz
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Patent number: 9793393Abstract: A semiconductor device includes a substrate, an active gate trench in the substrate; a source polysilicon pickup trench in the substrate; a polysilicon electrode disposed in the source polysilicon pickup trench; and a body region in the substrate. The top surface of the polysilicon electrode is below the bottom of the body region.Type: GrantFiled: September 23, 2013Date of Patent: October 17, 2017Assignee: Alpha and Omega Semiconductor IncorporatedInventors: John Chen, Il Kwan Lee, Hong Chang, Wenjun Li, Anup Bhalla, Hamza Yilmaz
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Publication number: 20140091386Abstract: A semiconductor device includes a substrate, an active gate trench in the substrate; a source polysilicon pickup trench in the substrate; a polysilicon electrode disposed in the source polysilicon pickup trench; and a body region in the substrate. The top surface of the polysilicon electrode is below the bottom of the body region.Type: ApplicationFiled: September 23, 2013Publication date: April 3, 2014Applicant: Alpha and Omega Semiconductor IncorporatedInventors: John Chen, Il Kwan Lee, Hong Chang, Wenjun Li, Anup Bhalla, Hamza Yilmaz
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Patent number: 8564055Abstract: A semiconductor device includes a substrate, an active gate trench in the substrate, the active gate trench has a first top gate electrode and a first bottom source electrode, and a gate runner trench comprising a second top gate electrode and a second bottom source electrode. The second top gate electrode is narrower than the second bottom source electrode.Type: GrantFiled: April 26, 2012Date of Patent: October 22, 2013Assignee: Alpha and Omega Semiconductor IncorporatedInventors: John Chen, Il Kwan Lee, Hong Chang, Wenjun Li, Anup Bhalla, Hamza Yilmaz
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Patent number: 8354334Abstract: A method is disclosed for forming a patterned thick metallization atop a semiconductor chip wafer. The method includes fabricating a nearly complete semiconductor chip wafer ready for metallization; depositing a bottom metal layer of sub-thickness TK1 together with its built-in alignment mark using a hot metal process; depositing a top metal layer of sub-thickness TK2 using a cold metal process thus forming a stacked thick metallization of total thickness TK=TK1+TK2; then, use the built-in alignment mark as reference, patterning the stacked thick metallization. A patterned thick metallization is thus formed with the advantages of better metal step coverage owing to the superior step coverage nature of the hot metal process as compared to the cold metal process; and lower alignment error rate owing to the lower alignment signal noise nature of the cold metal process as compared to the hot metal process.Type: GrantFiled: October 21, 2011Date of Patent: January 15, 2013Assignee: Alpha & Omega Semiconductor Inc.Inventor: Il Kwan Lee
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Patent number: 8288273Abstract: A method is disclosed for forming a patterned thick metallization atop a semiconductor chip wafer. The method includes fabricating a nearly complete semiconductor chip wafer ready for metallization; depositing a bottom metal layer of sub-thickness TK1 together with its built-in alignment mark using a hot metal process; depositing a top metal layer of sub-thickness TK2 using a cold metal process thus forming a stacked thick metallization of total thickness TK=TK1+TK2; then, use the built-in alignment mark as reference, patterning the stacked thick metallization. A patterned thick metallization is thus formed with the advantages of better metal step coverage owing to the superior step coverage nature of the hot metal process as compared to the cold metal process; and lower alignment error rate owing to the lower alignment signal noise nature of the cold metal process as compared to the hot metal process.Type: GrantFiled: October 17, 2011Date of Patent: October 16, 2012Assignee: Alpha & Omega Semiconductor Inc.Inventor: Il Kwan Lee
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Publication number: 20120205737Abstract: A semiconductor device includes a substrate, an active gate trench in the substrate, the active gate trench has a first top gate electrode and a first bottom source electrode, and a gate runner trench comprising a second top gate electrode and a second bottom source electrode. The second top gate electrode is narrower than the second bottom source electrode.Type: ApplicationFiled: April 26, 2012Publication date: August 16, 2012Applicant: ALPHA AND OMEGA SEMICONDUCTOR INCInventors: John Chen, Il Kwan Lee, Hong Chang, Wenjun Li, Anup Bhalla, Hamza Yilmaz
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Patent number: 8236651Abstract: A method for fabricating a semiconductor device includes forming a plurality of trenches, including applying a first mask, forming a first polysilicon region in at least some of the plurality of trenches, forming a inter-polysilicon dielectric region and a termination protection region, including applying a second mask, forming a second polysilicon region in the at least some of the plurality of trenches, forming a first electrical contact to the first polysilicon region and forming a second electrical contact to the second polysilicon region, including applying a third mask, disposing a metal layer, and forming a source metal region and a gate metal region, including applying a fourth mask.Type: GrantFiled: August 14, 2009Date of Patent: August 7, 2012Assignee: Alpha and Omega Semiconductor IncorporatedInventors: John Chen, Il Kwan Lee, Hong Chang, Wenjun Li, Anup Bhalla, Hamza Yilmaz
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Patent number: 8193580Abstract: A semiconductor device embodiment includes a substrate, an active gate trench in the substrate, and an asymmetric trench in the substrate. The asymmetric trench has a first trench wall and a second trench wall, the first trench wall is lined with oxide having a first thickness, and the second trench wall is lined with oxide having a second thickness that is different from the first thickness. Another semiconductor device embodiment includes a substrate, an active gate trench in the substrate; and a source polysilicon pickup trench in the substrate. The source polysilicon pickup trench includes a polysilicon electrode, and top surface of the polysilicon electrode is below a bottom of a body region. Another semiconductor device includes a substrate, an active gate trench in the substrate, the active gate trench has a first top gate electrode and a first bottom source electrode, and a gate runner trench comprising a second top gate electrode and a second bottom source electrode.Type: GrantFiled: August 14, 2009Date of Patent: June 5, 2012Assignee: Alpha and Omega Semiconductor, Inc.Inventors: John Chen, Il Kwan Lee, Hong Chang, Wenjun Li, Anup Bhalla, Hamza Yilmaz
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Publication number: 20120037981Abstract: A method is disclosed for forming a patterned thick metallization atop a semiconductor chip wafer. The method includes fabricating a nearly complete semiconductor chip wafer ready for metallization; depositing a bottom metal layer of sub-thickness TK1 together with its built-in alignment mark using a hot metal process; depositing a top metal layer of sub-thickness TK2 using a cold metal process thus forming a stacked thick metallization of total thickness TK=TK1+TK2; then, use the built-in alignment mark as reference, patterning the stacked thick metallization. A patterned thick metallization is thus formed with the advantages of better metal step coverage owing to the superior step coverage nature of the hot metal process as compared to the cold metal process; and lower alignment error rate owing to the lower alignment signal noise nature of the cold metal process as compared to the hot metal process.Type: ApplicationFiled: October 21, 2011Publication date: February 16, 2012Inventor: Il Kwan Lee
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Publication number: 20120034775Abstract: A method is disclosed for forming a patterned thick metallization atop a semiconductor chip wafer. The method includes fabricating a nearly complete semiconductor chip wafer ready for metallization; depositing a bottom metal layer of sub-thickness TK1 together with its built-in alignment mark using a hot metal process; depositing a top metal layer of sub-thickness TK2 using a cold metal process thus forming a stacked thick metallization of total thickness TK=TK1+TK2; then, use the built-in alignment mark as reference, patterning the stacked thick metallization. A patterned thick metallization is thus formed with the advantages of better metal step coverage owing to the superior step coverage nature of the hot metal process as compared to the cold metal process; and lower alignment error rate owing to the lower alignment signal noise nature of the cold metal process as compared to the hot metal process.Type: ApplicationFiled: October 17, 2011Publication date: February 9, 2012Inventor: Il Kwan Lee
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Patent number: 8067304Abstract: A method is disclosed for forming a patterned thick metallization atop a semiconductor chip wafer. The method includes fabricating a nearly complete semiconductor chip wafer ready for metallization; depositing a bottom metal layer of sub-thickness TK1 together with its built-in alignment mark using a hot metal process; depositing a top metal layer of sub-thickness TK2 using a cold metal process thus forming a stacked thick metallization of total thickness TK=TK1+TK2; then, use the built-in alignment mark as reference, patterning the stacked thick metallization. A patterned thick metallization is thus formed with the advantages of better metal step coverage owing to the superior step coverage nature of the hot metal process as compared to the cold metal process; and lower alignment error rate owing to the lower alignment signal noise nature of the cold metal process as compared to the hot metal process.Type: GrantFiled: January 20, 2009Date of Patent: November 29, 2011Assignee: Alpha and Omega Semiconductor, Inc.Inventor: Il Kwan Lee
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Publication number: 20110037120Abstract: A semiconductor device embodiment includes a substrate, an active gate trench in the substrate, and an asymmetric trench in the substrate. The asymmetric trench has a first trench wall and a second trench wall, the first trench wall is lined with oxide having a first thickness, and the second trench wall is lined with oxide having a second thickness that is different from the first thickness. Another semiconductor device embodiment includes a substrate, an active gate trench in the substrate; and a source polysilicon pickup trench in the substrate. The source polysilicon pickup trench includes a polysilicon electrode, and top surface of the polysilicon electrode is below a bottom of a body region. Another semiconductor device includes a substrate, an active gate trench in the substrate, the active gate trench has a first top gate electrode and a first bottom source electrode, and a gate runner trench comprising a second top gate electrode and a second bottom source electrode.Type: ApplicationFiled: August 14, 2009Publication date: February 17, 2011Inventors: John Chen, Il Kwan Lee, Hong Chang, Wenjun Li, Anup Bhalla, Hamza Yilmaz
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Publication number: 20110039383Abstract: A method for fabricating a semiconductor device includes forming a plurality of trenches, including applying a first mask, forming a first polysilicon region in at least some of the plurality of trenches, forming a inter-polysilicon dielectric region and a termination protection region, including applying a second mask, forming a second polysilicon region in the at least some of the plurality of trenches, forming a first electrical contact to the first polysilicon region and forming a second electrical contact to the second polysilicon region, including applying a third mask, disposing a metal layer, and forming a source metal region and a gate metal region, including applying a fourth mask.Type: ApplicationFiled: August 14, 2009Publication date: February 17, 2011Inventors: John Chen, Il Kwan Lee, Hong Chang, Wenjun Li, Anup Bhalla, Hamza Yilmaz
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Publication number: 20100181617Abstract: A method is disclosed for forming a patterned thick metallization atop a semiconductor chip wafer. The method includes fabricating a nearly complete semiconductor chip wafer ready for metallization; depositing a bottom metal layer of sub-thickness TK1 together with its built-in alignment mark using a hot metal process; depositing a top metal layer of sub-thickness TK2 using a cold metal process thus forming a stacked thick metallization of total thickness TK=TK1+TK2; then, use the built-in alignment mark as reference, patterning the stacked thick metallization. A patterned thick metallization is thus formed with the advantages of better metal step coverage owing to the superior step coverage nature of the hot metal process as compared to the cold metal process; and lower alignment error rate owing to the lower alignment signal noise nature of the cold metal process as compared to the hot metal process.Type: ApplicationFiled: January 20, 2009Publication date: July 22, 2010Inventor: Il Kwan Lee
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Patent number: 7683369Abstract: A structure is disclosed for measuring body pinch resistance Rp of trench MOSFET arrays on a wafer. The trench MOSFET array has a common drain layer of first conductivity type and a 2D-trench MOSFET array atop the common drain layer. The 2D-trench MOSFET array has an interdigitated array of source-body columns and gate trench columns. Each source-body column has a bottom body region of second conductivity type with up-extending finger structures. Each source-body column has top source regions of first conductivity type bridging the finger structures. The structure includes: a) A source-body column wherein each finger structure of the bottom body region has a formed top contact electrode. b) Two gate trench columns flank the source-body column and both have a formed top common gate contact electrode. Upon connection of the structure to external voltage/current measurement devices, Rp can be measured while mimicking the parasitic effect of neighboring trench MOSFETs.Type: GrantFiled: April 10, 2008Date of Patent: March 23, 2010Assignee: Alpha & Omega Semiconductor, Inc.Inventors: Moses Ho, Tiesheng Li, Il Kwan Lee
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Publication number: 20090256149Abstract: A structure is disclosed for measuring body pinch resistance Rp of trench MOSFET arrays on a wafer. The trench MOSFET array has a common drain layer of first conductivity type and a 2D-trench MOSFET array atop the common drain layer. The 2D-trench MOSFET array has an interdigitated array of source-body columns and gate trench columns. Each source-body column has a bottom body region of second conductivity type with up-extending finger structures. Each source-body column has top source regions of first conductivity type bridging the finger structures. The structure includes: a) A source-body column wherein each finger structure of the bottom body region has a formed top contact electrode. b) Two gate trench columns flank the source-body column and both have a formed top common gate contact electrode. Upon connection of the structure to external voltage/current measurement devices, Rp can be measured while mimicking the parasitic effect of neighboring trench MOSFETs.Type: ApplicationFiled: April 10, 2008Publication date: October 15, 2009Inventors: Moses Ho, Tiesheng Li, Il Kwan Lee