Patents by Inventor Il-Hun Son

Il-Hun Son has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7697249
    Abstract: A clamping circuit is provided, which may clamp a voltage at a node of a circuit to a stable level by using a transistor already included in the circuit. The clamping circuit may clamp a voltage at a first node of a circuit inside a semiconductor chip to a more stable level when electro-static discharge (ESD) occurs. The clamping circuit may include a transistor and a capacitive element to store a control voltage to turn on the transistor in response to ESD.
    Type: Grant
    Filed: December 28, 2006
    Date of Patent: April 13, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyoung-Sik Im, Han-Gu Kim, Jae-Hyok Ko, Il-Hun Son, Suk-Jin Kim
  • Patent number: 7319347
    Abstract: Provided are a bi-directional high voltage switching device that includes an N-channel double diffused metal oxide semiconductor field effect transistor (DMOS FET) and a P-channel DMOS FET, each conducting current bi-directionally, and an energy recovery circuit that reduces the amount of energy consumed when charging or discharging a load capacitor by efficiently driving the bi-directional high voltage switching device; where the N-channel symmetric DMOS FET and the P-channel symmetric DMOS FET are connected to each other in parallel; and the energy recovery circuit includes a pull-up device, a pull-down device, an energy recovery capacitor, and a bi-directional high voltage switching device.
    Type: Grant
    Filed: December 21, 2004
    Date of Patent: January 15, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yoon-Jay Cho, Il-Hun Son, Jae-Il Byeon
  • Publication number: 20070177329
    Abstract: A clamping circuit is provided, which may clamp a voltage at a node of a circuit to a stable level by using a transistor already included in the circuit. The clamping circuit may clamp a voltage at a first node of a circuit inside a semiconductor chip to a more stable level when electro-static discharge (ESD) occurs. The clamping circuit may include a transistor and a capacitive element to store a control voltage to turn on the transistor in response to ESD.
    Type: Application
    Filed: December 28, 2006
    Publication date: August 2, 2007
    Inventors: Kyoung-Sik Im, Han-Gu Kim, Jae-Hyok Ko, Il-Hun Son, Suk-Jin Kim
  • Publication number: 20050161733
    Abstract: Provided are a bi-directional high voltage switching device that includes an N-channel double diffused metal oxide semiconductor field effect transistor (DMOS FET) and a P-channel DMOS FET, each conducting current bi-directionally, and an energy recovery circuit that reduces the amount of energy consumed when charging or discharging a load capacitor by efficiently driving the bi-directional high voltage switching device; where the N-channel symmetric DMOS FET and the P-channel symmetric DMOS FET are connected to each other in parallel; and the energy recovery circuit includes a pull-up device, a pull-down device, an energy recovery capacitor, and a bi-directional high voltage switching device.
    Type: Application
    Filed: December 21, 2004
    Publication date: July 28, 2005
    Inventors: Yoon-Jay Cho, Il-Hun Son, Jae-Il Byeon