Abstract: Certain aspects of the present disclosure provide a circuit for clock signal generation. The circuit generally includes a plurality of clock generation circuits configured to generate a plurality of clock signals from a clock signal, and a power supply circuit having an output coupled to power supply inputs of the plurality of clock generation circuits. The circuit may also include a capacitor array coupled to the output of the power supply circuit and include a plurality of capacitive elements, the capacitor array being configured to selectively couple each of the plurality of capacitive elements to the output of the power supply circuit based on a quantity of one or more active clock generation circuits of the plurality of clock generation circuits.

Abstract: An apparatus is disclosed for implementing multi-mode oscillation circuitry with stepping control. In an example aspect, the multi-mode oscillation circuitry comprises a resonator coupled to a first oscillator and a second oscillator. The multi-mode oscillation circuitry is configured to selectively be in a first configuration with the first oscillator in an active state and the second oscillator in an inactive state or a second configuration with the first oscillator in the inactive state and the second oscillator in the active state. The apparatus also includes a step-control circuit coupled to the multi-mode oscillation circuitry. The step-control circuit is configured to cause the first oscillator to switch from the inactive state to the active state and incrementally increase a first gain of the first oscillator based on the first oscillator being in the active state to enable the multi-mode oscillation circuitry to transition from the second configuration to the first configuration.

Abstract: An apparatus is disclosed for implementing multi-mode oscillation circuitry with stepping control. In an example aspect, the multi-mode oscillation circuitry comprises a resonator coupled to a first oscillator and a second oscillator. The multi-mode oscillation circuitry is configured to selectively be in a first configuration with the first oscillator in an active state and the second oscillator in an inactive state or a second configuration with the first oscillator in the inactive state and the second oscillator in the active state. The apparatus also includes a step-control circuit coupled to the multi-mode oscillation circuitry. The step-control circuit is configured to cause the first oscillator to switch from the inactive state to the active state and incrementally increase a first gain of the first oscillator based on the first oscillator being in the active state to enable the multi-mode oscillation circuitry to transition from the second configuration to the first configuration.

Abstract: Power conservation in a phase locked loop (PLL) places the PLL into a low-power mode and periodically reactivates the PLL to prevent leakage current from causing a voltage controlled oscillator (VCO) within the PLL to drift. The PLL also includes an adjustable delay circuit positioned between an output of the VCO and an input of a phase detector, where the delay circuit is used to adjust phase slew of a feedback signal to help the PLL settle into a desired frequency. By controlling the drift of the VCO and keeping the phase slew of the feedback signal to a minimum, the PLL may be activated and settle to a desired frequency within a relatively short amount of time. By keeping this time so short, the PLL may be placed into and pulled out of a low-power mode and still meet rigid timing requirements of various transmission protocols.

Abstract: Power conservation in a phase locked loop (PLL) places the PLL into a low-power mode and periodically reactivates the PLL to prevent leakage current from causing a voltage controlled oscillator (VCO) within the PLL to drift. The PLL also includes an adjustable delay circuit positioned between an output of the VCO and an input of a phase detector, where the delay circuit is used to adjust phase slew of a feedback signal to help the PLL settle into a desired frequency. By controlling the drift of the VCO and keeping the phase slew of the feedback signal to a minimum, the PLL may be activated and settle to a desired frequency within a relatively short amount of time. By keeping this time so short, the PLL may be placed into and pulled out of a low-power mode and still meet rigid timing requirements of various transmission protocols.

Abstract: An apparatus is disclosed for hybrid-controlled clock generation. In an example aspect, the apparatus includes an analog control circuit, a digital control circuit, a transistor array, an oscillator circuit, and a selection circuit. The oscillator circuit is coupled to the transistor array. The selection circuit includes a first input that is coupled to the analog control circuit, a second input that is coupled to the digital control circuit, and an output that is coupled to the transistor array. The selection circuit is configured to obtain a selection signal that is indicative of the first input coupled to the analog control circuit or the second input coupled to the digital control circuit. The selection circuit is also configured to connect, based on the selection signal, the analog control circuit or the digital control circuit to the transistor array.

Abstract: An apparatus is disclosed for hybrid-controlled clock generation. In an example aspect, the apparatus includes an analog control circuit, a digital control circuit, a transistor array, an oscillator circuit, and a selection circuit. The oscillator circuit is coupled to the transistor array. The selection circuit includes a first input that is coupled to the analog control circuit, a second input that is coupled to the digital control circuit, and an output that is coupled to the transistor array. The selection circuit is configured to obtain a selection signal that is indicative of the first input coupled to the analog control circuit or the second input coupled to the digital control circuit. The selection circuit is also configured to connect, based on the selection signal, the analog control circuit or the digital control circuit to the transistor array.

Abstract: A narrow pulse filter is disclosed. The narrow pulse filter includes a first tri-state inverter. The narrow pulse filter further includes a pulse generator coupled to the first tri-state inverter. The pulse generator is configured to cause the first tri-state inverter to enter a high-impedance state to filter out a narrow pulse from a signal input to the first tri-state inverter.