Patents by Inventor Ilya Osadchiy
Ilya Osadchiy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11825209Abstract: Learning-based color correction (e.g., auto while balance (AWB)) procedures may be trained based on datasets from different sensors using a pre-processing procedure. Each input pixel may be converted into a sensor-independent representation through multiplication by a sensor-specific color conversion function (e.g., a 3×3 matrix). The sensor-specific color conversion function may be obtained based on a sensor type. For example, the sensor-specific color conversion function, such as a 3×3 matrix, may be obtained by a corresponding sensor calibration procedure performed using laboratory images of a color checker chart subject to standard illuminants. Parameters of the sensor-specific color conversion function may be optimized in a chromaticity space. For instance, a sensor-specific 3×3 matrix for color conversion may be optimized using a distance in the chromaticity space between calibration data (e.g., calibration configurations) and sensor-independent targets (e.g.Type: GrantFiled: July 15, 2022Date of Patent: November 21, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ilya Osadchiy, Doron Sabo
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Publication number: 20220377297Abstract: Learning-based color correction (e.g., auto while balance (AWB)) procedures may be trained based on datasets from different sensors using a pre-processing procedure. Each input pixel may be converted into a sensor-independent representation through multiplication by a sensor-specific color conversion function (e.g., a 3×3 matrix). The sensor-specific color conversion function may be obtained based on a sensor type. For example, the sensor-specific color conversion function, such as a 3×3 matrix, may be obtained by a corresponding sensor calibration procedure performed using laboratory images of a color checker chart subject to standard illuminants. Parameters of the sensor-specific color conversion function may be optimized in a chromaticity space. For instance, a sensor-specific 3×3 matrix for color conversion may be optimized using a distance in the chromaticity space between calibration data (e.g., calibration configurations) and sensor-independent targets (e.g.Type: ApplicationFiled: July 15, 2022Publication date: November 24, 2022Inventors: Ilya OSADCHIY, Doron SABO
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Publication number: 20220141438Abstract: Learning-based color correction (e.g., auto while balance (AWB)) procedures may be trained based on datasets from different sensors using a pre-processing procedure. Each input pixel may be converted into a sensor-independent representation through multiplication by a sensor-specific color conversion function (e.g., a 3×3 matrix). The sensor-specific color conversion function (e.g., the 3×3 matrix) may be obtained based on a sensor type. For example, the sensor-specific color conversion function, such as a 3×3 matrix, may be obtained by a corresponding sensor calibration procedure performed using laboratory images of a color checker chart subject to standard illuminants. Parameters of the sensor-specific color conversion function may be optimized in a chromaticity space. For instance, a sensor-specific 3×3 matrix for color conversion may be optimized using a distance in the chromaticity space between calibration data (e.g., calibration configurations) and sensor-independent targets (e.g.Type: ApplicationFiled: November 5, 2020Publication date: May 5, 2022Inventors: Ilya Osadchiy, Doron Sabo
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Patent number: 11275637Abstract: A processor of an aspect includes an instruction pipeline to process a multiple memory address instruction that indicates multiple memory addresses. The processor also includes multiple page fault aggregation logic coupled with the instruction pipeline. The multiple page fault aggregation logic is to aggregate page fault information for multiple page faults that are each associated with one of the multiple memory addresses of the instruction. The multiple page fault aggregation logic is to provide the aggregated page fault information to a page fault communication interface. Other processors, apparatus, methods, and systems are also disclosed.Type: GrantFiled: August 14, 2020Date of Patent: March 15, 2022Assignee: Intel CorporationInventors: Boris Ginzburg, Ronny Ronen, Ilya Osadchiy
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Publication number: 20200379835Abstract: A processor of an aspect includes an instruction pipeline to process a multiple memory address instruction that indicates multiple memory addresses. The processor also includes multiple page fault aggregation logic coupled with the instruction pipeline. The multiple page fault aggregation logic is to aggregate page fault information for multiple page faults that are each associated with one of the multiple memory addresses of the instruction. The multiple page fault aggregation logic is to provide the aggregated page fault information to a page fault communication interface. Other processors, apparatus, methods, and systems are also disclosed.Type: ApplicationFiled: August 14, 2020Publication date: December 3, 2020Inventors: Boris Ginzburg, Ronny Ronen, Ilya Osadchiy
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Publication number: 20190205200Abstract: A processor of an aspect includes an instruction pipeline to process a multiple memory address instruction that indicates multiple memory addresses. The processor also includes multiple page fault aggregation logic coupled with the instruction pipeline. The multiple page fault aggregation logic is to aggregate page fault information for multiple page faults that are each associated with one of the multiple memory addresses of the instruction. The multiple page fault aggregation logic is to provide the aggregated page fault information to a page fault communication interface. Other processors, apparatus, methods, and systems are also disclosed.Type: ApplicationFiled: December 27, 2018Publication date: July 4, 2019Inventors: Boris Ginzburg, Ronny Ronen, Ilya Osadchiy
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Patent number: 10255126Abstract: A processor of an aspect includes an instruction pipeline to process a multiple memory address instruction that indicates multiple memory addresses. The processor also includes multiple page fault aggregation logic coupled with the instruction pipeline. The multiple page fault aggregation logic is to aggregate page fault information for multiple page faults that are each associated with one of the multiple memory addresses of the instruction. The multiple page fault aggregation logic is to provide the aggregated page fault information to a page fault communication interface. Other processors, apparatus, methods, and systems are also disclosed.Type: GrantFiled: February 12, 2018Date of Patent: April 9, 2019Assignee: Intel CorporationInventors: Boris Ginzburg, Ronny Ronen, Ilya Osadchiy
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Publication number: 20180181458Abstract: A processor of an aspect includes an instruction pipeline to process a multiple memory address instruction that indicates multiple memory addresses. The processor also includes multiple page fault aggregation logic coupled with the instruction pipeline. The multiple page fault aggregation logic is to aggregate page fault information for multiple page faults that are each associated with one of the multiple memory addresses of the instruction. The multiple page fault aggregation logic is to provide the aggregated page fault information to a page fault communication interface. Other processors, apparatus, methods, and systems are also disclosed.Type: ApplicationFiled: February 12, 2018Publication date: June 28, 2018Applicant: lntel CorporationInventors: Boris Ginzburg, Ronny Ronen, Ilya Osadchiy
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Patent number: 9891980Abstract: A processor of an aspect includes an instruction pipeline to process a multiple memory address instruction that indicates multiple memory addresses. The processor also includes multiple page fault aggregation logic coupled with the instruction pipeline. The multiple page fault aggregation logic is to aggregate page fault information for multiple page faults that are each associated with one of the multiple memory addresses of the instruction. The multiple page fault aggregation logic is to provide the aggregated page fault information to a page fault communication interface. Other processors, apparatus, methods, and systems are also disclosed.Type: GrantFiled: December 29, 2011Date of Patent: February 13, 2018Assignee: Intel CorporationInventors: Boris Ginzburg, Ronny Ronen, Ilya Osadchiy
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Patent number: 9892481Abstract: A thread on one processor may be used to enable another processor to lock or release a mutex. For example, a central processing unit thread may be used by a graphics processing unit to secure a mutex for a shared memory.Type: GrantFiled: September 28, 2016Date of Patent: February 13, 2018Assignee: Intel CorporationInventors: Boris Ginzburg, Esfirush Natanzon, Ilya Osadchiy, Yoav Zach
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Patent number: 9720730Abstract: In one embodiment, the present invention includes a multicore processor with first and second groups of cores. The second group can be of a different instruction set architecture (ISA) than the first group or of the same ISA set but having different power and performance support level, and is transparent to an operating system (OS). The processor further includes a migration unit that handles migration requests for a number of different scenarios and causes a context switch to dynamically migrate a process from the second core to a first core of the first group. This dynamic hardware-based context switch can be transparent to the OS. Other embodiments are described and claimed.Type: GrantFiled: December 30, 2011Date of Patent: August 1, 2017Assignee: Intel CorporationInventors: Boris Ginzburg, Ilya Osadchiy, Ronny Ronen, Eliezer Weissmann, Michael Mishaeli, Alon Naveh, David A. Koufaty, Scott D. Hahn, Tong Li, Avi Mendleson, Eugene Gorbatov, Hisham Abu-Salah, Dheeraj R. Subbareddy, Paolo Narvaez, Aamer Jaleel, Efraim Rotem, Yuval Yosef, Anil Aggarwal, Kenzo Van Craeynest
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Patent number: 9633407Abstract: A thread on one processor may be used to enable another processor to lock or release a mutex. For example, a central processing unit thread may be used by a graphics processing unit to secure a mutex for a shared memory.Type: GrantFiled: July 29, 2011Date of Patent: April 25, 2017Assignee: Intel CorporationInventors: Boris Ginzburg, Esfirush Natanzon, Ilya Osadchiy, Yoav Zach
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Publication number: 20170018051Abstract: A thread on one processor may be used to enable another processor to lock or release a mutex. For example, a central processing unit thread may be used by a graphics processing unit to secure a mutex for a shared memory.Type: ApplicationFiled: September 28, 2016Publication date: January 19, 2017Inventors: Boris Ginzburg, Esfir Natanzon, Ilya Osadchiy, Yoav Zach
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Publication number: 20140304559Abstract: A processor of an aspect includes an instruction pipeline to process a multiple memory address instruction that indicates multiple memory addresses. The processor also includes multiple page fault aggregation logic coupled with the instruction pipeline. The multiple page fault aggregation logic is to aggregate page fault information for multiple page faults that are each associated with one of the multiple memory addresses of the instruction. The multiple page fault aggregation logic is to provide the aggregated page fault information to a page fault communication interface. Other processors, apparatus, methods, and systems are also disclosed.Type: ApplicationFiled: December 29, 2011Publication date: October 9, 2014Inventors: Boris Ginzburg, Ronny Ronen, Ilya Osadchiy
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Publication number: 20140082630Abstract: In one embodiment, the present invention includes a multicore processor with first and second groups of cores. The second group can be of a different instruction set architecture (ISA) than the first group or of the same ISA set but having different power and performance support level, and is transparent to an operating system (OS). The processor further includes a migration unit that handles migration requests for a number of different scenarios and causes a context switch to dynamically migrate a process from the second core to a first core of the first group. This dynamic hardware-based context switch can be transparent to the OS. Other embodiments are described and claimed.Type: ApplicationFiled: December 30, 2011Publication date: March 20, 2014Inventors: Boris Ginzburg, Ilya Osadchiy, Ronny Ronen, Eliezer Weissmann, Michael Mishaeli, Alon Naveh, David A. Koufaty, Scott D. Hahn, Tong Li, Avi Mendleson, Eugene Gorbatov, Hisham Abu-Salah, Dheeraj R. Subbareddy, Paolo Narvaez, Aamer Jaleel, Efraim Rotem, Yuval Yosef, Anil Aggarwal, Kenzo Van Craeynest
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Publication number: 20130027410Abstract: A thread on one processor may be used to enable another processor to lock or release a mutex. For example, a central processing unit thread may be used by a graphics processing unit to secure a mutex for a shared memory.Type: ApplicationFiled: July 29, 2011Publication date: January 31, 2013Inventors: Boris Ginzburg, Esfirush Natanzon, Ilya Osadchiy, Yoav Zach
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Publication number: 20120236010Abstract: Page faults arising in a graphics processing unit may be handled by an operating system running on the central processing unit. In some embodiments, this means that unpinned memory can be used for the graphics processing unit. Using unpinned memory in the graphics processing unit may expand the capabilities of the graphics processing unit in some cases.Type: ApplicationFiled: March 15, 2011Publication date: September 20, 2012Inventors: Boris Ginzburg, Esfir Natanzon, Ilya Osadchiy, Ronny Ronen, Eliezer Weissmann, Yoav Zach, Robert L. Farrell
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Publication number: 20120233439Abstract: Page faults arising in a graphics processing unit may be handled by an operating system running on the central processing unit. In some embodiments, this means that unpinned memory can be used for the graphics processing unit. Using unpinned memory in the graphics processing unit may expand the capabilities of the graphics processing unit in some cases.Type: ApplicationFiled: March 11, 2011Publication date: September 13, 2012Inventors: Boris Ginzburg, Esfir Natanzon, Ilya Osadchiy, Ronny Ronen, Eliezer Weissmann, Yoav Zach, Robert L. Farrell