Abstract: The DRAM cell includes a first transistor, a second transistor, and a capacitor. The first and second transistors each have a gate, a source, and a drain electrode. The gate electrode of the second transistor is connected to one of the source and drain electrodes of the first transistor, and a first electrode of the capacitor is connected to the gate electrode of the second transistor. Also, a second electrode of the capacitor is connected to one of the source and drain electrodes of the second transistor. One of the source and drain electrodes of the second transistor not connected to the second electrode of the capacitor is connected to the gate electrode of the second transistor. Accordingly, the second transistor is on when a logic value of "1" is stored in the gate thereof, and off when a logic value of `0` is stored in the gate thereof.

Abstract: A process for preparing a semiconductor device using a dielectric thin film includes the steps of forming a first electrode on a base plate; forming a dielectric film on the first electrode, the dielectric film including a Perovskite structure oxide; forming a second electrode on the dielectric film; and annealing the first and second electrodes so that metal components of the first and second electrodes are oxidized and diffused into a crystal system of the dielectric film.

Abstract: An electron gun for a color cathode ray tube includes cathode, control and screen electrodes, forming a triode. The electron gun includes first, second and third focus electrodes, forming main and auxiliary lenses. A final accelerating electrode faces the third focus electrode. A static voltage is applied to the screen electrode and the second focus electrode. A dynamic focus voltage is applied to the first and third focus electrodes. First and second quadrupole lenses are formed.

Abstract: An electrode structure and fabrication method for a capacitor for a semiconductor memory device which have been improved suitably for the formation of a high dielectric thin film, which method includes forming an interlayer insulation film on a substrate having a transistor formed therein, forming an electrode material on the interlayer insulation layer, forming a resist on the electrode material for patterning the electrode material, forming a lower electrode each surface of which has the same slope with respect to the substrate by performing an isotropic etching on the electrode material having the resist pattern thereon and the resist, forming a dielectric film on the lower electrode to have a regular thickness, and forming an upper electrode on the dielectric film to have a regular thickness.

Abstract: The DRAM cell includes a first transistor, a second transistor, and a capacitor. The first and second transistors each have a gate, a source, and a drain electrode. The gate electrode of the second transistor is connected to one of the source and drain electrodes of the first transistor, and a first electrode of the capacitor is connected to the gate electrode of the second transistor. Also, a second electrode of the capacitor is connected to one of the source and drain electrodes of the second transistor. One of the source and drain electrodes of the second transistor not connected to the second electrode of the capacitor is connected to the gate electrode of the second transistor. Accordingly, the second transistor is on when a logic value of "1" is stored in the gate thereof, and off when a logic value of `0` is stored in the gate thereof.

Abstract: A method for fabricating a capacitor for a semiconductor device includes the steps of depositing an insulating layer on a substrate, selectively removing the insulating layer and forming a first contact hole, forming a conductive semiconductor layer in the contact hole to a predetermined depth, selectively removing the insulating layer adjacent the first contact hole and forming a second contact hole, forming a first electrode in the second contact hole, forming a dielectric thin film on the first electrode, and forming a second electrode on the dielectric thin film.

Abstract: A method for fabricating a capacitor for a semiconductor device includes the steps of depositing an insulating layer on a substrate, selectively removing the insulating layer and forming a contact hole, forming a first electrode in the contact hole, removing the insulating layer to expose a portion of the first electrode, and sequentially forming a dielectric layer and a second electrode on the exposed portion of the first electrode.

Abstract: The DRAM cell includes a first transistor, a second transistor, and a capacitor. The first and second transistors each have a gate, a source, and a drain electrode. The gate electrode of the second transistor is connected to one of the source and drain electrodes of the first transistor, and a first electrode of the capacitor is connected to the gate electrode of the second transistor. Also, a second electrode of the capacitor is connected to one of the source and drain electrodes of the second transistor. One of the source and drain electrodes of the second transistor not connected to the second electrode of the capacitor is connected to the gate electrode of the second transistor. Accordingly, the second transistor is on when a logic value of "1" is stored in the gate thereof, and off when a logic value of `0` is stored in the gate thereof.

Abstract: A method for fabricating a semiconductor memory element which has an excellent insulation property suitable for high density integration, including the steps of forming self-aligning plate electrodes by etching a dielectric film covering an upperside protective layer by an amount sufficient to expose each of the dielectric films, forming a third insulation film the entire surface thereof, exposing the upperside protection layer by etching the third insulation film with photosensitive films used as masks, forming a bit line contact by etching the upperside protection layer and the underside protection layer until the impurity region through the bit line contact.