Abstract: A power transmission apparatus of a hybrid electric vehicle may include an input shaft receiving an engine torque, an output shaft disposed at a same axis with the input shaft and outputting a shifted torque, first and second motor/generators, a first shifting section including a compound planetary gear set formed as a combination of first and second planetary gear sets, forming an adjusted torque from the engine torque received through two paths and torques of the first and second motor/generators, and outputting the adjusted torque, and a second shifting section including a third planetary gear set and outputting a shifted torque of two stages from a torque received from the first shifting section to the output shaft.

Abstract: A semiconductor device includes a fin-type pattern extending in a first direction, a device isolation film surrounding the fin-type pattern, while exposing an upper portion of the fin-type pattern, a gate electrode extending on the device isolation film and the fin-type pattern in a second direction intersecting the first direction, a gate isolation film isolating the gate electrode in the second direction, and including a first material and on the device isolation film, an interlayer insulating film filling a side surface of the fin-type pattern and including a second material different from the first material.

Abstract: A display device capable of setting an optimal output enable value according to a color pattern and a method for driving the display device. A timing controller is configured to receive an image signal from an external source, identify a color pattern and set an output enable value corresponding to the identified color pattern. A scan driver is configured to receive the output enable value and generate a first scan signal having a first turn-on signal and a second scan signal adjacent to the first scan signal and having a second turn-on signal. The scan driver may adjust an interval between the first turn-on signal and the second turn-on signal based on the output enable value.

Abstract: A display apparatus includes a gate driving control circuit, a gate driver and a display panel. The gate driving control circuit generates N gate clock signals and N inversion gate clock signals based on N gate clock control signals, phases of which partially overlap with each other. Each inversion gate clock signals has an opposite phase to a respective gate clock signal. The gate driver generates gate signals based on the N gate clock signals or the N inversion gate clock signals and applies the gate signals to gate lines. The display panel includes pixels, each connected to a respective gate line and a respective data line. Each of the pixels has a longer side in parallel with gate lines and a shorter side in parallel with the data lines. A number of the gate clock control signals is an integer multiple of a number of colors of the pixels.

Abstract: A power control method and an electronic device and/or connecting unit to implement the power control method is provided. The electronic device includes a first interface unit configured to be connected to an external device that can receive and provide power to the electronic device, a second interface unit configured to be connected to an external charger that can provide power for the external device and the electronic device, and a main controller configured to detect whether or not the external charger is connected, and receive and direct power from the external device or the external charger according to whether or not the external charger is connected.

Abstract: A display device includes a display panel, and a power management circuit including a switching regulator for supplying a power in a discontinuous conduction mode or in a continuous conduction mode, and a sensing circuit for sensing whether the switching regulator is operated in the discontinuous conduction mode, the switching regulator including a comparator for monitoring the supplied power, and an RS latch for receiving an output signal from the comparator, and the sensing circuit including a phase lock loop circuit for generating a first clock signal, a phase delay circuit for generating a second clock signal having a phase delayed from the first, and a determination circuit for outputting a first value when a pulse width of the output signal from the RS latch is small, and for outputting a second value when the pulse width of the output signal from the RS latch is not small.

Abstract: A semiconductor device includes a fin-type pattern extending in a first direction, a device isolation film surrounding the fin-type pattern, while exposing an upper portion of the fin-type pattern, a gate electrode extending on the device isolation film and the fin-type pattern in a second direction intersecting the first direction, a gate isolation film isolating the gate electrode in the second direction, and including a first material and on the device isolation film, an interlayer insulating film filling a side surface of the fin-type pattern and including a second material different from the first material.

Abstract: A semiconductor device includes channel layers on a substrate, the channel layers being spaced apart from each other, and having first side surfaces and second side surfaces opposing each other in a first direction, a gate electrode surrounding the channel layers and having a first end portion and a second end portion, opposing each other in the first direction, and a source/drain layer on a first side of the gate electrode and in contact with the channel layers, a portion of the source/drain layer protruding further than the first end portion of the gate electrode in the first direction, wherein a first distance from the first end portion of the gate electrode to the first side surfaces of the channel layers is shorter than a second distance from the second end portion of the gate electrode to the second side surfaces of the channel layers.

Abstract: A power transmission apparatus of a hybrid electric vehicle may include an input shaft receiving an engine torque output from an engine, an output shaft disposed at a same axis with the input shaft and outputting a shifted torque, first and second motor/generators, a first shifting section including a first planetary gear set, outputting a rotation speed from the input shaft as inputted or increased, or forming an adjusted torque from the engine torque and torques of the first and second motor/generators, and outputting the adjusted torque, and a second shifting section including a compound planetary gear set formed as a combination of second and third planetary gear sets and outputting a shifted torque at least three stages from a torque received from the first shifting section to the output shaft.

Abstract: A power transmission apparatus of a hybrid electric vehicle may include an input shaft receiving an engine torque, an output shaft disposed at a same axis with the input shaft and outputting a shifted torque, first and second motor/generators, a first shifting section including a compound planetary gear set formed as a combination of first and second planetary gear sets, forming an adjusted torque from the engine torque received through two paths and torques of the first and second motor/generators, and outputting the adjusted torque, and a second shifting section including a third planetary gear set and outputting a shifted torque of two stages from a torque received from the first shifting section to the output shaft.

Abstract: In a method of manufacturing a stack package, a first semiconductor chip is formed on a first package substrate. A second semiconductor chip is formed on a second package substrate. A plurality of signal pads and a thermal diffusion member are formed on a lower surface and/or an upper surface of an interposer substrate, the signal pad having a first height and the thermal diffusion member having a second height greater than the first height. The first package substrate, the interposer substrate, and the second package substrate are sequentially stacked on one another such that the thermal diffusion member is in contact with an upper surface of the first semiconductor chip or a lower surface of the second package substrate.

Abstract: A semiconductor device includes a fin-type pattern extending in a first direction, a device isolation film surrounding the fin-type pattern, while exposing an upper portion of the fin-type pattern, a gate electrode extending on the device isolation film and the fin-type pattern in a second direction intersecting the first direction, a gate isolation film isolating the gate electrode in the second direction, and including a first material and on the device isolation film, an interlayer insulating film filling a side surface of the fin-type pattern and including a second material different from the first material.

Abstract: A semiconductor package includes a first semiconductor package including a first substrate and a lower semiconductor chip mounted on the first substrate, a second semiconductor package stacked on the first semiconductor package and including a second substrate and an upper semiconductor chip mounted on the second substrate, and an interposer substrate interposed between the first semiconductor package and the second semiconductor package and having a recess recessed from a lower surface facing the lower semiconductor chip, wherein the interposer substrate includes a dummy wiring layer disposed to be adjacent to the recess, in a region overlapped with the lower semiconductor chip, and no electrical signal is applied to the dummy wiring layer.

Abstract: A display apparatus includes a display panel, a gate driver and a data driver. The display panel displays an image. The gate driver outputs gate signals to the display panel. The data driver outputs data voltages to the display panel. The data driver includes a plurality of data driving circuits. At least two data driving circuits among the data driving circuits have different turn off timings or different turn on timings in a vertical blank period.

Abstract: Disclosed are a thermoplastic resin composition including about 100 parts by weight of a base resin including (A-1) about 50 wt % to about 70 wt % of a polycarbonate resin and (A-2) about 30 wt % to about 50 wt % of a rubber modified vinyl-based copolymer, (B) about 1 to about 3 parts by weight of a cross-linkable styrene-acrylonitrile copolymer; and (C) about 1 to about 3 parts by weight of a methyl methacrylate-butyl acrylate copolymer, and a molded article using the same.

Abstract: A semiconductor package includes a first semiconductor package including a first substrate and a lower semiconductor chip mounted on the first substrate, a second semiconductor package stacked on the first semiconductor package and including a second substrate and an upper semiconductor chip mounted on the second substrate, and an interposer substrate interposed between the first semiconductor package and the second semiconductor package and having a recess recessed from a lower surface facing the lower semiconductor chip, wherein the interposer substrate includes a dummy wiring layer disposed to be adjacent to the recess, in a region overlapped with the lower semiconductor chip, and no electrical signal is applied to the dummy wiring layer.

Abstract: A thermoplastic resin composition of the present invention comprises: an acrylate-based rubber-modified vinyl-based graft copolymer; aromatic vinyl-cyanide vinyl-based copolymer resin; a first dulling agent; and a second dulling agent, wherein the first dulling agent is a copolymer (PS-g-SAN) in which a styrene-acrylonitrile copolymer is graft-polymerized in polystyrene, and the second dulling agent is a copolymer in which a styrene-acrylonitrile copolymer is graft-polymerized in a poly(ethylene-co-glycidyl methacrylate). The thermoplastic resin composition has excellent low-light properties, impact resistance and fluidity.

Abstract: A clock generation circuit includes: a clock generator to receive a gate pulse signal and to generate at least one gate clock signal corresponding to the gate pulse signal; an over-current protector to detect a current level of the at least one gate clock signal, and to output a shutdown enable signal and at least one switching signal corresponding to the detected current level; and a switching unit including at least one switching device to output the gate pulse signal as the at least one gate clock signal. The clock generator is to generate the at least one gate clock signal in response to the shutdown enable signal, and the at least one switching device is to transmit the gate pulse signal as the at least one gate clock signal in response to the at least one switching signal.

Abstract: A simulation method includes receiving a netlist describing a plurality of devices, performing an arithmetic operation by using values of random telegraph signal (RTS) noise factors respectively corresponding to the plurality of devices, generating an RTS model corresponding to each of the devices, based on a result of the arithmetic operation, and generating a netlist in which the RTS model is reflected.

Abstract: A display device includes a display panel, and a power management circuit including a switching regulator for supplying a power in a discontinuous conduction mode or in a continuous conduction mode, and a sensing circuit for sensing whether the switching regulator is operated in the discontinuous conduction mode, the switching regulator including a comparator for monitoring the supplied power, and an RS latch for receiving an output signal from the comparator, and the sensing circuit including a phase lock loop circuit for generating a first clock signal, a phase delay circuit for generating a second clock signal having a phase delayed from the first, and a determination circuit for outputting a first value when a pulse width of the output signal from the RS latch is small, and for outputting a second value when the pulse width of the output signal from the RS latch is not small.