Abstract: An eco-friendly power source such as a battery module is provided for a transportation vehicle, including: a first sub-module and a second sub-module respectively including a cell stack in which a plurality of battery cells are stacked; and a central wall disposed between the first sub-module and the second sub-module, wherein the central wall includes a first central wall facing the first sub-module and a second central wall facing the second sub-module, wherein the first central wall has a rotationary symmetrical shape of the second central wall around a first axis.

Abstract: A manufacturing method of a catalyst may modify a carbon layer structure by using various heat treatment gases such as inert gas (Ar), hydrogen, and carbon monoxide in a carbon layer manufacturing process, thereby optimizing the carbon layer structure according to the purpose of a metal without changing a size of the metal.

Abstract: A 3D memory device, the device including: a first structure including a plurality of memory cells, where each memory cell of the plurality of memory cells includes at least one memory transistor, where each of the at least one memory transistor includes a source, a drain, and a channel; a plurality of memory-line pillars, where each memory-line pillar of the plurality of memory-line pillars is directly connected to a plurality of the source or the drain, where the plurality of memory-line pillars are vertically oriented, and where the at least one memory transistor is self-aligned to an overlaying another the at least one memory transistor, both being processed following a same lithography step; and a control level including a memory controller circuit, where the memory controller circuit includes a row buffer, where the control level is bonded to the first structure, and where the bonded includes hybrid bonding.

Abstract: In one example, a semiconductor device can comprise a substrate, a device stack, first and second internal interconnects, and an encapsulant. The substrate can comprise a first and second substrate sides opposite each other, a substrate outer sidewall between the first substrate side and the second substrate side, and a substrate inner sidewall defining a cavity between the first substrate side and the second substrate side. The device stack can be in the cavity and can comprise a first electronic device, and a second electronic device stacked on the first electronic device. The first internal interconnect can be coupled to the substrate and the device stack. The encapsulant can cover the substrate inner sidewall and the device stack and can fill the cavity. Other examples and related methods are disclosed herein.

Abstract: Provided is an organic light emitting device comprising a light emitting layer comprising an organic alloy of a compound of Chemical Formula 1 and a compound of Chemical Formula 2, the device having improved driving voltage, efficiency, and lifespan: where A is a benzene ring fused with the two adjacent rings, X1, X2 and X3 are each independently CH or N, provided that at least one of X1, X2 and X3 is N, Ar1-Ar5 are each independently a substituted or unsubstituted C6-60 aryl or a substituted or unsubstituted C2-60 heteroaryl containing at least one of N, O and S, and the other substituents are defined in the specification, provided that at least one of Ar4 and Ar5 is substituted with at least one deuterium, or at least one R2 is deuterium.

Abstract: A 3D device, the device including: at least one first level including logic circuits; at least one second level bonded to the first level, where the at least one second level includes a plurality of transistors; connectivity structures, where the connectivity structures include a plurality of transmission lines, where the plurality of transmission lines are designed to conduct radio frequencies (“RF”) signals, and where the bonded includes oxide to oxide bond regions and metal to metal bond regions; and a plurality of vias disposed through the at least one second level, where at least a majority of the plurality of vias have a diameter of less than 5 micrometers.

Abstract: A 3D semiconductor device including: a first level including a single crystal layer, and a memory control circuit which includes at least one temperature sensor circuit and first transistors; a first metal layer overlaying the first single crystal layer; a second metal layer overlaying the first metal layer; a third metal layer overlaying the second metal layer; second transistors—which may include a metal gate—disposed atop the third metal layer; third transistors disposed atop the second transistors; a fourth metal layer disposed atop the third transistors; a memory array including word-lines and at least four memory mini arrays (each mini array includes at least four rows by four columns of memory cells), each memory cell includes at least one second transistor or at least one third transistor; and a connection path from fourth metal to third metal, the path includes a via disposed through the memory array.

Abstract: A display device includes a data conductive layer including a first power line, a passivation layer with a first opening exposing the first power line, a via layer with a second opening partially overlapping the first opening, a pixel electrode on the via layer, a connection electrode in the first and second openings, a pixel-defining film with an opening overlapping the second opening, a light-emitting layer on the pixel-defining film, the pixel electrode and the connection electrode, and a common electrode connected to the first power line. The data conductive layer includes a data base layer, a data main metal layer, and a data capping layer, the first power line includes a wire connection structure, in which the data main metal layer is recessed from sides of the data capping layer, and the common electrode is connected to the data main metal layer in the wire connection structure.

Abstract: Provided a semiconductor memory device. The semiconductor memory device includes a substrate, a gate electrode on the substrate, a bit line on the substrate, a cell semiconductor pattern on a side of the gate electrode and electrically connected to the bit line, a capacitor structure including a first electrode electrically connected to the cell semiconductor pattern, a second electrode on the first electrode, and a capacitor dielectric film between the first electrode and the second electrode, a bit line strapping line spaced apart from the bit line in the second direction, and electrically connected to the bit line, a bit line selection line between the bit line and the bit line strapping line, and a selection semiconductor pattern between the bit line and the bit line strapping line and electrically connected to all of the bit line, the bit line strapping line, and the bit line selection line.

Abstract: A transistor array substrate includes a substrate, an active layer disposed on the substrate and including a channel region, a source region and a drain region, a gate insulating layer disposed on a part of the active layer, a gate electrode overlapping the channel region of the active layer and included in an electrode conductive layer which is disposed on the gate insulating layer, a source electrode included in the electrode conductive layer and in contact with a part of the source region of the active layer, and a drain electrode included in the electrode conductive layer and in contact with a part of the drain region of the active layer. The active layer includes an oxide semiconductor including crystals and is disposed as an island shape excluding a hole in a plan view.

Abstract: A device, including: a first structure including first memory cells, the first memory cells including first transistors; and a second structure including second memory cells, the second memory cells including second transistors, where the second transistors overlay the first transistors, and a plurality of memory cells control lines, where the first transistors are self-aligned to the second transistors, where a second transistor channel of the second transistors is aligned to a first transistor channel of the first transistors, the aligned is at an atomic level as would have been resulted from an epitaxial growth process.

Abstract: Discussed is an organic light emitting device in which a light emitting layer includes a host and different kinds of dopants, the fluorescent dopant is formed of a material having energy level properties facilitating thermally activated delayed fluorescence (TADF), and thus energy is concentratedly transferred to the fluorescent dopant so as to increase luminous efficacy of a single color.

Abstract: Proposed is a heat dissipating device using turbulent flow. In the heat dissipating device, a plurality of block flow paths are formed in parallel inside a block body, a first cap and a second cap are mounted on side surfaces of the respective ends of the block body so as to connect the block flow paths, a working fluid flows into the block flow paths, and the working fluid which has passed through the block flow paths is transferred to the outside. Turbulence generators are mounted inside the block flow paths, and finishing end portions on the respective ends of the turbulence generators are supported by the first cap and the second cap and are positioned inside the block flow paths.

Abstract: An organic light emitting device comprising an anode, a cathode, and a light emitting layer between the anode and the cathode, the light emitting layer including an organic alloy of a compound represented by Chemical Formula 1 and a compound represented by Chemical Formula 2, and having improved driving voltage, efficiency and lifetime.

Abstract: An organic light emitting device comprising an anode, a cathode, and a light emitting layer between the anode and the cathode, the light emitting layer including a compound represented by the following Chemical Formula 1 and a compound represented by the following Chemical Formula 2, is provided.

Abstract: An organic light emitting device having improved efficiency, driving voltage, and lifespan is provided. The organic light emitting device comprises an anode, a cathode, and a light emitting between the anode and the cathode, and the light emitting layer comprises a first compound represented by Chemical Formula 1 and a second compound represented by Chemical Formula 2.

Abstract: The present invention relates to a high voltage-type redox flow battery comprising: a plurality of modules (1001, 1002, 1003, . . , 100n) which are serially connected; and a battery management system (BMS) for monitoring a state-of-charge (SOC) of each of the plurality of modules (1001, 1002, 1003, ..

Abstract: An organic light emitting device comprising an anode, a cathode, and a light emitting layer between the anode and the cathode, the light emitting layer including an organic alloy of a compound represented by Chemical Formula 1 and a compound represented by Chemical Formula 2, and having improved driving voltage, efficiency and lifetime.

Abstract: The method includes forming a first dielectric layer on a substrate, forming a via in the first dielectric layer, sequentially forming a first metal pattern, a first metal oxide pattern, a second metal pattern, and an antireflective pattern on the first dielectric layer, and performing an annealing process to react the first metal oxide pattern and the second metal pattern with each other to form a second metal oxide pattern. The forming the second metal oxide pattern includes forming the second metal oxide pattern by a reaction between a metal element of the second metal pattern and an oxygen element of the first metal oxide pattern.

Abstract: An all-printed physically unclonable function based on a single-walled carbon nanotube network. The network may be a mixture of semiconducting and metallic nanotubes randomly tangled with each other through the printing process. The unique distribution of carbon nanotubes in a network can be used for authentication, and this feature can be a secret key for a high level hardware security. The carbon nanotube network does not require any advanced purification process, alignment of nanotubes, high-resolution lithography and patterning. Rather, the intrinsic randomness of carbon nanotubes is leveraged to provide the unclonable aspect.