Abstract: A first-order signal generator (135). The generator comprises a shift register (210?) having a number N of bit positions. Each bit position is operable to store a binary value, the shift register operable to shift the binary value at each of the bit positions. The generator also comprises circuitry for tapping selected ones of the bit positions and circuitry for applying a function (220?) to each binary value in the selected ones of the bit positions to provide a function output. The generator also comprises circuitry for coupling the function output as an input to one of the bit positions. Lastly, the generator also comprises circuitry (230?) for outputting a first-order noise signal by coupling, as a twos complement number, each binary value in a plurality of the bit positions.

Abstract: A first-order signal generator (135). The generator comprises a shift register (210?) having a number N of bit positions. Each bit position is operable to store a binary value, the shift register operable to shift the binary value at each of the bit positions. The generator also comprises circuitry for tapping selected ones of the bit positions and circuitry for applying a function (220?) to each binary value in the selected ones of the bit positions to provide a function output. The generator also comprises circuitry for coupling the function output as an input to one of the bit positions.

Abstract: A method and apparatus for processing pulse code modulation (PCM) data that do not reach the full dynamic range of a transmission bus. The method and apparatus provide an output processed PCM data having the maximum peak signal allowable by a transmission bus. The output signal limitation is also dependent on a sampling or recording frequency of input signals. In view of the sampling or recording frequency, the invention scales the processing of the PCM data accordingly.

Abstract: A conversion system and method is disclosed for converting between digital and analog data signals. The conversion system comprises a signal input line for each digital data signal, a reconstructor-resampler unit for each digital data signal, a combiner, a modulator, a digital-to-analog converter, and a signal output line. Each signal line input couples to the respective reconstructor-resampler unit for the digital data signal. Each reconstructor-resampler unit then couples to a combiner which couples to a modulator. The modulator couples to the digital-to-analog converter that couples to the signal output line from which an analog output signal is produced. The reconstructor-resampler comprises a sampling member coupled to the signal line input and a polynomial interpolator member coupled to the sampling member and the modulator. Also, the modulator operates at a predetermined, or fixed, frequency regardless of the sampling frequency of the digital data signal.