Abstract: A semiconductor package includes an interposer including a first redistribution layer and a second redistribution layer that is on the first redistribution layer and is electrically coupled to the first redistribution layer; and a semiconductor chip on the interposer. The first redistribution layer includes a first organic insulating layer and a plurality of first conductors in the first organic insulating layer. The second redistribution layer includes a second organic insulating layer, a first silicon insulating layer on the second organic insulating layer, and a plurality of second conductors penetrating through both the second organic insulating layer and the first silicon insulating layer. The semiconductor chip includes a second silicon insulating layer and a plurality of third conductors in the second silicon insulating layer.

Abstract: The present disclosure provides semiconductor packages including a heat dissipation structure. In some embodiments, the semiconductor package includes a package substrate, a stacked chip disposed on the package substrate and including a lower chip and an upper chip, a memory chip disposed on the package substrate adjacent to the stacked chip, and an encapsulant encapsulating at least a portion of the stacked chip and the memory chip on the package substrate. An upper surface of the upper chip is exposed from the encapsulant. A dummy silicon chip is in contact with the upper chip on the lower chip.

Abstract: A semiconductor package includes: a first package substrate including a first redistribution structure; a second package substrate including a second redistribution structure; a semiconductor chip provided between the first package substrate and the second package substrate, and attached to the first package substrate; and a fiducial mark provided on the second package substrate and separated from the second redistribution structure in a plan view.

Abstract: A semiconductor package includes a base structure having a fan-in area and fan-out areas surrounding the fan-in area, a semiconductor chip in the fan-in area, a package body layer in the fan-in area and the fan-out areas and covering the semiconductor chip, a redistribution structure on the package body layer, and alignment marks on the redistribution structure in a plan view. Each of the alignment marks includes a plurality of metal layers, and a plurality of auxiliary patterns are in the redistribution structure under the alignment marks to assist in recognition of the alignment marks.

Abstract: A semiconductor device including a first lower buffer chip, an upper buffer chip disposed on an upper surface of the first lower buffer chip, a plurality of conductive posts spaced apart from the first lower buffer chip and disposed on a lower surface of the upper buffer chip, and a first memory chip stack structure disposed on the upper buffer chip and including a plurality of first memory chips.

Abstract: A semiconductor package includes a redistribution wiring layer having a first surface and a second surface opposite to the first surface, a conductive bump on the first surface, and a first semiconductor device on the conductive bump. The redistribution wiring layer includes redistribution wirings having an uppermost redistribution wiring, a bonding pad, and an uppermost insulating layer. The uppermost redistribution wiring has a redistribution via and a redistribution line on the redistribution via. The bonding pad disposes on the redistribution line of the uppermost redistribution wiring, and the conductive bump is disposed on the bonding pad. The uppermost insulating layer overlapping (e.g., covering) the uppermost redistribution wiring and having an opening exposing a portion of the bonding pad.

Abstract: A semiconductor package includes a first semiconductor device on a first redistribution substrate, a first mold layer that covers the first semiconductor device and the first redistribution substrate, and a second redistribution substrate on the first mold layer, the second redistribution substrate including a first opening that exposes a top surface of the first mold layer, a sidewall of the second redistribution substrate that is exposed to the first opening having a stepwise structure.

Abstract: Disclosed are packages and their fabrication methods. The package includes: a lower substrate with an upper pad; a lower chip on the lower substrate; a mold layer on the lower chip and the lower substrate; a post extending through the mold layer and provided on the upper pad around the lower chip, the post having a diameter less than a diameter of the upper pad; and an upper substrate on the post and the mold layer, the upper substrate including a lower pad having a diameter greater than the diameter of the post.

Abstract: A semiconductor package includes: an encapsulation layer sealing at least one semiconductor chip; a redistribution level layer arranged on the encapsulation layer; a laser mark metal layer arranged on the redistribution level layer; and a laser mark arranged inside the laser mark metal layer. The laser mark includes letters, numbers, figures, symbols, and recognition codes indicating various pieces of information of the semiconductor package.

Abstract: A semiconductor package includes a substrate including a redistribution layer, a chip structure including a first semiconductor chip disposed on the substrate and including a first through-electrode, a second semiconductor chip disposed on the first semiconductor chip and electrically connected to the first semiconductor chip by the first through-electrode, and a first encapsulant at least partially surrounding the second semiconductor chip. A first connection bump disposed between the substrate and the chip structure and electrically connects the first through-electrode to the redistribution layer, a second connection bump disposed below the substrate and electrically connects to the redistribution layer, and a second encapsulant e the chip structure on the substrate. The first semiconductor chip is connected to and faces the second semiconductor chip.

Abstract: A semiconductor package includes a package substrate, a semiconductor stack on the package substrate, a passive device on the package substrate and spaced apart from the semiconductor stack, and a stiffener on the package substrate and extending around an outer side of the semiconductor stack. The stiffener includes a first step surface extends over the passive device. A width of a bottom surface of the stiffener is smaller than a width of a top surface of the stiffener.

Abstract: A semiconductor package includes a base substrate; a redistribution substrate disposed on the base substrate, and that includes first insulating layers and redistribution pattern layers disposed on the first insulating layers, respectively; a semiconductor chip disposed on the redistribution substrate and electrically connected to the redistribution pattern layers; and a chip structure disposed on the redistribution substrate adjacent to the semiconductor chip and electrically connected to the semiconductor chip through the redistribution pattern layers, wherein the semiconductor chip includes a body that has an active surface that faces the redistribution substrate; first and second contact pads spaced apart from each other below the active surface; a first bump structure and a passive device electrically connected to the first connection pad at a lower level from the first connection pad; and a second bump structure electrically connected to the second connection pad at a lower level from the second connect

Abstract: A semiconductor package includes a first semiconductor device on a first redistribution substrate, a first mold layer that covers the first semiconductor device and the first redistribution substrate, and a second redistribution substrate on the first mold layer, the second redistribution substrate including a first opening that exposes a top surface of the first mold layer, a sidewall of the second redistribution substrate that is exposed to the first opening having a stepwise structure.