Abstract: Apparatus, methods, media and systems for multiple sets of trim parameters are described. A non-volatile memory device may comprise a first register, a second register, a multiplexer, a first set of I/O lines, each coupled to the first register and the multiplexer, each associated with a particular trim set among multiple trim sets stored in the first register, one or more second I/O lines, each coupled to the second register and the multiplexer. The multiplexer is configured to receive a control signal. The multiplexer is configured to output, based on the control signal, a particular trim set among the multiple trim sets to the second register using the one or more second I/O lines.

Abstract: Apparatus, methods, media and systems for multiple sets of trim parameters are described. A non-volatile memory device may comprise a first register, a second register, a multiplexer, a first set of I/O lines, each coupled to the first register and the multiplexer, each associated with a particular trim set among multiple trim sets stored in the first register, one or more second I/O lines, each coupled to the second register and the multiplexer. The multiplexer is configured to receive a control signal. The multiplexer is configured to output, based on the control signal, a particular trim set among the multiple trim sets to the second register using the one or more second I/O lines.

Abstract: Apparatus, methods, media and systems for multiple sets of trim parameters are described. A non-volatile memory device may comprise a first register, a second register, a multiplexer, a first set of I/O lines, each coupled to the first register and the multiplexer, each associated with a particular trim set among multiple trim sets stored in the first register, one or more second I/O lines, each coupled to the second register and the multiplexer. The multiplexer is configured to receive a control signal. The multiplexer is configured to output, based on the control signal, a particular trim set among the multiple trim sets to the second register using the one or more second I/O lines.

Abstract: Apparatus, methods, media and systems for multiple sets of trim parameters are described. A non-volatile memory device may comprise a first register, a second register, a multiplexer, a first set of I/O lines, each coupled to the first register and the multiplexer, each associated with a particular trim set among multiple trim sets stored in the first register, one or more second I/O lines, each coupled to the second register and the multiplexer. The multiplexer is configured to receive a control signal. The multiplexer is configured to output, based on the control signal, a particular trim set among the multiple trim sets to the second register using the one or more second I/O lines.

Abstract: Apparatus, methods, media and systems for multiple sets of trim parameters are described. A non-volatile memory device may comprise a first register, a second register, a multiplexer, a first set of I/O lines, each coupled to the first register and the multiplexer, each associated with a particular trim set among multiple trim sets stored in the first register, one or more second I/O lines, each coupled to the second register and the multiplexer. The multiplexer is configured to receive a control signal. The multiplexer is configured to output, based on the control signal, a particular trim set among the multiple trim sets to the second register using the one or more second I/O lines.

Abstract: Apparatus, methods, media and systems for multiple sets of trim parameters are described. A non-volatile memory device may comprise a first register, a second register, a multiplexer, a first set of I/O lines, each coupled to the first register and the multiplexer, each associated with a particular trim set among multiple trim sets stored in the first register, one or more second I/O lines, each coupled to the second register and the multiplexer. The multiplexer is configured to receive a control signal. The multiplexer is configured to output, based on the control signal, a particular trim set among the multiple trim sets to the second register using the one or more second I/O lines.

Abstract: A method to perform a lossless synchronization software reset is disclosed including provisions for monitoring an arrangement for occurrence of a software reset condition; saving at least one arrangement parameter in a memory in the arrangement; performing at least one software reset on the arrangement; performing a device mount procedure; reading the at least one arrangement parameter in the memory and initializing at least one component according to the at least one arrangement parameter saved in the memory.

Abstract: A method to perform a lossless synchronization software reset is disclosed including provisions for monitoring an arrangement for occurrence of a software reset condition; saving at least one arrangement parameter in a memory in the arrangement; performing at least one software reset on the arrangement; performing a device mount procedure; reading the at least one arrangement parameter in the memory and initializing at least one component according to the at least one arrangement parameter saved in the memory.

Abstract: Systems and methods for detecting a command execution abort are disclosed. Power failure may abort the writing of data in a memory device prematurely, resulting in potential data corruption. A memory device controller in the memory device sends commands, such as write or erase commands, to one or more memory integrated circuit chips. Along with executing the commands, the memory integrated circuit chips track execution of the commands by storing the address at which the command is being executed along with flag(s) indicative of the progress executing the command (e.g., command has begun and/or completed execution). When a power failure occurs, the memory device controller may poll the memory integrated circuit chips for the address/flags information to determine whether (or where) the command abort occurred. Thus, relying on the address/flag(s), the memory device controller may more quickly or easily determine whether a command abort has occurred.

Abstract: A nonvolatile memory that stores boot data from a host learns which data is boot data by monitoring read commands received from a host during a powering up operation. Boot data is then arranged in a manner that makes subsequent reading of the boot data faster when it is accessed during a subsequent powering up operation.

Abstract: Systems and methods for detecting a command execution abort are disclosed. Power failure may abort the writing of data in a memory device prematurely, resulting in potential data corruption. A memory device controller in the memory device sends commands, such as write or erase commands, to one or more memory integrated circuit chips. Along with executing the commands, the memory integrated circuit chips track execution of the commands by storing the address at which the command is being executed along with flag(s) indicative of the progress executing the command (e.g., command has begun and/or completed execution). When a power failure occurs, the memory device controller may poll the memory integrated circuit chips for the address/flags information to determine whether (or where) the command abort occurred. Thus, relying on the address/flag(s), the memory device controller may more quickly or easily determine whether a command abort has occurred.

Abstract: Systems and methods for detecting a command execution abort are disclosed. Power failure may abort the writing of data in a memory device prematurely, resulting in potential data corruption. A memory device controller in the memory device sends commands, such as write or erase commands, to one or more memory integrated circuit chips. Along with executing the commands, the memory integrated circuit chips track execution of the commands by storing the address at which the command is being executed along with flag(s) indicative of the progress executing the command (e.g., command has begun and/or completed execution). When a power failure occurs, the memory device controller may poll the memory integrated circuit chips for the address/flags information to determine whether (or where) the command abort occurred. Thus, relying on the address/flag(s), the memory device controller may more quickly or easily determine whether a command abort has occurred.

Abstract: In one embodiment, a memory system is provided comprising a volatile memory, a non-volatile memory, and an error correction code (ECC) module. The ECC module is configured to encode, decode, and correct data stored in the volatile memory when the memory system enters and exits a sleep mode and is further configured to encode, decode, and correct data stored in the non-volatile memory when the memory system is in an active mode.

Abstract: Systems and methods for detecting a command execution abort are disclosed. Power failure may abort the writing of data in a memory device prematurely, resulting in potential data corruption. A memory device controller in the memory device sends commands, such as write or erase commands, to one or more memory integrated circuit chips. Along with executing the commands, the memory integrated circuit chips track execution of the commands by storing the address at which the command is being executed along with flag(s) indicative of the progress executing the command (e.g., command has begun and/or completed execution). When a power failure occurs, the memory device controller may poll the memory integrated circuit chips for the address/flags information to determine whether (or where) the command abort occurred. Thus, relying on the address/flag(s), the memory device controller may more quickly or easily determine whether a command abort has occurred.

Abstract: A storage device with a memory may have an alternative safe mode boot loading process. Upon detecting a malfunction, the storage device may activate a safe mode in which a safe mode boot loader is stored in memory of the storage device that is not logically mapped. The safe mode allows for recovery and debugging by the host that may not otherwise be possible without the safe mode process.

Abstract: A memory system and method for securing volatile memory during sleep mode using the same ECC module used to secure non-volatile memory during active mode are provided. In one embodiment, a memory system is provided comprising a volatile memory, a non-volatile memory, and an error correction code (ECC) module. The ECC module is configured to encode, decode, and correct data stored in the volatile memory when the memory system enters and exits a sleep mode and is further configured to encode, decode, and correct data stored in the non-volatile memory when the memory system is in an active mode. Other embodiments are possible.

Abstract: A system and method are disclosed for an electronic integrated circuit to communicate with different hosts via different interfaces using the same host protocol. The system may use a host interface circuit to select a first set of electrical contacts or a second set of electrical contacts in order for a first host or a second host, respectively, to communicate with the electronic integrated circuit using a host protocol. The method may include switching from communicating with the first host using the first set of electrical contacts to communicating with the second host using the second set of electrical contacts in order for the second host to test the electronic integrated circuit.

Abstract: A pulmonary measurement system includes a pulmonary measurement device that includes a mouthpiece with an airflow path and a sensor positioned in the airflow path; and a controller communicably coupled to the sensor. The controller includes a processor and instructions stored in memory and is operable to execute the instructions with the processor to perform operations including identifying a measurement from the sensor; identifying a particular equation stored in the memory, the particular equation developed using data analytics and including an input parameter that is based on the identified measurement; and based on the identified measurement and the particular equation, determining a value of absolute lung volume.

Abstract: A nonvolatile memory that stores boot data from a host learns which data is boot data by monitoring read commands received from a host during a powering up operation. Boot data is then arranged in a manner that makes subsequent reading of the boot data faster when it is accessed during a subsequent powering up operation.

Abstract: A system and method are disclosed for an electronic integrated circuit to communicate with different hosts via different interfaces using the same host protocol. The system may use a host interface circuit to select a first set of electrical contacts or a second set of electrical contacts in order for a first host or a second host, respectively, to communicate with the electronic integrated circuit using a host protocol. The method may include switching from communicating with the first host using the first set of electrical contacts to communicating with the second host using the second set of electrical contacts in order for the second host to test the electronic integrated circuit.