Abstract: A capacitor structure includes a first lower conductive pattern, a first capacitor, a first upper conductive pattern, a second lower conductive pattern, a second capacitor and a second upper conductive pattern. The first capacitor includes first lower electrodes, first upper electrodes and first dielectric structures. Each of the first dielectric structures are disposed between one of the first lower electrodes and a corresponding one of the first upper electrodes. The first upper conductive pattern is formed on and is electrically connected to the first upper electrodes. The second lower conductive pattern is spaced apart from the first lower conductive pattern disposed on the substrate. The second capacitor includes second lower electrodes, second upper electrodes and second dielectric structures. The second upper conductive pattern is formed on and is electrically connected to the second upper electrodes. The first and second conductive patterns are electrically insulated from each other.

Abstract: A semiconductor device includes a lower structure; a lower electrode on the lower structure; an upper electrode covering the lower electrode on the lower structure; and a dielectric structure disposed between the lower electrode and the upper electrode. The dielectric structure includes a first dielectric film including a first material and a second dielectric film including a second material different from the first material. The first dielectric film includes a first surface in contact with or facing the lower electrode and a second surface facing the first surface. The second dielectric film includes a first portion disposed in an opening of the first dielectric film and extending in a direction from the second surface toward the first surface.

Abstract: In a method of a method of depositing a layer, a substrate is loaded on a substrate stage within a chamber. A precursor gas and a reaction gas are alternately supplied into the chamber to form at least one atomic layer. A surface of the at least one atomic layer is planarized by applying pressure on the surface of the at least one atomic layer to diffuse atoms located on the surface having a relatively high curvature. The precursor gas and the reaction gas are alternately supplied into the chamber to form at least one atomic layer on the planarized atomic layer.

Abstract: A semiconductor device includes a substrate, a plurality of lower electrodes disposed on the substrate, at least one support layer in contact with the plurality of lower electrodes and extending in a direction, parallel to an upper surface of the substrate, an upper electrode disposed on the plurality of lower electrodes and the at least one support layer, a dielectric layer between the plurality of lower electrodes and the upper electrode and between the at least one support layer and the upper electrode, and a blocking layer disposed between the at least one support layer and the dielectric layer, and including a material having a bandgap energy greater than a bandgap energy of a material of the at least one support layer. The dielectric layer is in contact with the plurality of lower electrodes and is spaced apart from the at least one support layer by the blocking layer.

Abstract: A semiconductor memory device includes an interlayer insulating layer, a plurality of first contact pads embedded in the interlayer insulating layer, a plurality of first work function adjustment patterns embedded in the interlayer insulating layer and disposed on the plurality of first contact pads, and a plurality of lower electrodes disposed on the plurality of first work function adjustment patterns.

Abstract: A semiconductor device of the disclosure includes a substrate, a capacitor contact structure electrically connected to the substrate, a lower electrode connected to the capacitor contact structure, a capacitor insulating layer covering the lower electrode, and an upper electrode covering the capacitor insulating layer. The upper electrode includes a multiple layer on the capacitor insulating layer, and a cover layer on the multiple layer. The multiple layer includes a first electrode layer, a second electrode layer, and a first metal silicide layer between the first and second electrode layers. A work function of the first metal silicide layer is greater than a work function of the first electrode layer and a work function of the second electrode layer.

Abstract: A semiconductor device including a substrate, lower electrodes disposed on the substrate, at least one support layer in contact with the lower electrodes, a dielectric layer disposed on the lower electrodes, an upper electrode disposed on the dielectric layer, a first interfacial film between the lower electrodes and the dielectric layer, and a second interfacial film between the upper electrode and the dielectric layer. At least one of the first and second interfacial films includes a plurality of layers, wherein the plurality of layers include a first metal element, and a second metal element, and at least one of oxygen \and nitrogen. The lower electrodes include the first metal element. A first region of the first interfacial film includes the second metal element at a first concentration and a second region of the first interfacial film includes the second metal element at a second concentration different from the first concentration.

Abstract: A fabricating equipment and method for a semiconductor device is provided. The fabricating equipment comprises a process chamber including an internal space, a substrate support which supports a substrate including a first film and a second film, inside the internal space, a nozzle which is placed on the substrate support and supplies a process gas, a first heater which is placed inside the substrate support and heats the substrate and a second heater which generates one of waves of a first frequency and waves of a second frequency to differentially heat the first film and the second film.

Abstract: An integrated circuit semiconductor device includes a lower electrode formed on a substrate extending in a first direction and a second direction perpendicular to the first direction and a support structure supporting the lower electrode. The support structure includes a support pattern surrounding the lower electrode, extending in the first direction and the second direction, and having a hole through which the lower electrode passes, and a concavo-convex structure having at a surface of the support pattern a plurality of convex portions extending in a third direction perpendicular to the first direction and the second direction, and a plurality of concave portions arranged between the convex portions.

Abstract: An integrated circuit device includes: a lower electrode disposed on a substrate; an insulating support pattern supporting the lower electrode; a dielectric film surrounding the lower electrode and the insulating support pattern; a high-k interface layer arranged between the lower electrode and the dielectric film and between the insulating support pattern and the dielectric film, wherein the high-k interface layer contacts the insulating support pattern and includes a zirconium oxide layer; and an upper electrode disposed adjacent the lower electrode, wherein the high-k interface layer and the dielectric film are disposed between the upper electrode and the lower electrode.

Abstract: A semiconductor device is provided. The semiconductor device comprises a lower electrode, a lower dielectric layer on the lower electrode, an upper electrode on the lower dielectric layer, an upper dielectric layer formed between the lower dielectric layer and the upper electrode, and an interposed electrode film formed between the lower dielectric layer and the upper dielectric layer, wherein the upper dielectric layer includes titanium oxide.

Abstract: Carbon-based materials, and associated methods and articles, are generally provided. In some embodiments, a carbon-based material comprises a carbon-based portion and a functional group bonded to the carbon-based portion. The functional group may be capable of forming a reversible covalent bond with a species. Carbon may make up greater than or equal to 30 wt % of the carbon-based portion. The carbon-based portion may comprise graphene, and a ratio of a total number of functional groups in a plurality of functional groups bonded to the graphene to a total number of carbon atoms in the plurality of carbon atoms of the graphene may be greater than or equal to 1:50. The carbon-based portion may comprise graphene, and greater than or equal to 70% of the graphene sheets may be spaced apart from their nearest neighbors by a distance of greater than or equal to 10 ?. A method may comprise applying a voltage to a carbon-based material.

Abstract: Embodiments described herein generally relate to compositions including discrete nanostructures (e.g., nanostructures including a functionalized graphene layer and a core species bound to the functionalized graphene layer), and related articles and methods. A composition may have a coefficient of friction of less than or equal to 0.02. Discrete nanostructures may have a substantially non-planar configuration. A core species may reversibly covalently bind a first portion of a functionalized graphene layer to a second portion of the functionalized graphene layer. Articles, e.g., articles including a plurality of discrete nanostructures and a means for depositing the plurality of discrete nanostructures on a surface, are also provided. Methods (e.g., methods of forming a layer) are also provided, including depositing a composition onto a substrate surface and/or applying a mechanical force to the composition, e.g., such that the composition exhibits a coefficient of friction of less than or equal to 0.02.

Abstract: Embodiments described herein generally relate to compositions including discrete nanostructures (e.g., nanostructures including a functionalized graphene layer and a core species bound to the functionalized graphene layer), and related articles and methods. A composition may have a coefficient of friction of less than or equal to 0.02. Discrete nanostructures may have a substantially non-planar configuration. A core species may reversibly covalently bind a first portion of a functionalized graphene layer to a second portion of the functionalized graphene layer. Articles, e.g., articles including a plurality of discrete nanostructures and a means for depositing the plurality of discrete nanostructures on a surface, are also provided. Methods (e.g., methods of forming a layer) are also provided, including depositing a composition onto a substrate surface and/or applying a mechanical force to the composition, e.g., such that the composition exhibits a coefficient of friction of less than or equal to 0.02.

Abstract: Carbon-based materials, and associated methods and articles, are generally provided. In some embodiments, a carbon-based material comprises a carbon-based portion and a functional group bonded to the carbon-based portion. The functional group may be capable of forming a reversible covalent bond with a species. Carbon may make up greater than or equal to 30 wt % of the carbon-based portion. The carbon-based portion may comprise graphene, and a ratio of a total number of functional groups in a plurality of functional groups bonded to the graphene to a total number of carbon atoms in the plurality of carbon atoms of the graphene may be greater than or equal to 1:50. The carbon-based portion may comprise graphene, and greater than or equal to 70% of the graphene sheets may be spaced apart from their nearest neighbors by a distance of greater than or equal to 10 ?. A method may comprise applying a voltage to a carbon-based material.