Abstract: For data processing in a computing storage environment by a processor device, the computing storage environment incorporating at least high-speed and lower-speed caches, and tiered levels of storage, groups of data segments are migrated between the tiered levels of storage such that uniformly hot ones of the groups of data segments are migrated to utilize a Solid State Drive (SSD) portion of the tiered levels of storage, while sparsely hot ones of the groups of data segments are migrated to utilize the lower-speed cache.

Abstract: Dynamic administration of event pools for relevant event and alert analysis during event storms including receiving, by an events analyzer from an events queue, a plurality of events from one or more components of the distributed processing system, each event including an occurred time and a logged time; creating, by the event analyzer, an events pool; determining whether an arrival rate of the events from the components of the distributed processing system is greater than a predetermined threshold; if the arrival rate is greater than the predetermined threshold, assigning, by the events analyzer, a plurality of events to the events pool in dependence upon their occurred time; and if the arrival rate is not greater than the predetermined threshold, assigning, by the events analyzer, a plurality of events to the events pool in dependence upon their logged time.

Abstract: A heat exchanger core optimization method is provided for a heat exchanger door which resides at an air inlet or outlet side of an electronics rack, and includes an air-to-coolant heat exchanger with a heat exchanger core. The core includes a first coolant channel coupled to a coolant inlet manifold downstream from a second coolant channel, and the first channel has a shorter channel length than the second channel. Further, coolant channels of the core are coupled to provide counter-flow cooling of an airflow passing across the core. The core optimization method determines at least one combination of parameters that optimize for a particular application at least two performance metrics of the heat exchanger. This method includes obtaining performance metrics for boundary condition(s) of possible heat exchanger configurations with different variable parameters to determine a combination of parameters that optimize the performance metrics for the heat exchanger.

Abstract: Fencing data transfers in a parallel active messaging interface (‘PAMI’) of a parallel computer, the PAMI including data communications endpoints, each endpoint comprising a specification of data communications parameters for a thread of execution on a compute node, including specifications of a client, a context, and a task, the compute nodes coupled for data communications through the PAMI and through data communications resources including a deterministic data communications network, including initiating execution through the PAMI of an ordered sequence of active SEND instructions for SEND data transfers between two endpoints, effecting deterministic SEND data transfers; and executing through the PAMI, with no FENCE accounting for SEND data transfers, an active FENCE instruction, the FENCE instruction completing execution only after completion of all SEND instructions initiated prior to execution of the FENCE instruction for SEND data transfers between the two endpoints.

Abstract: A method, apparatus and decoder for decoding cyclic code are proposed. The decoding method comprises: receiving a transmitted cyclic code; calculating the initial syndrome of the cyclic code; by using the initial syndrome and w prestored successive shift operators, calculating respectively w successive shift syndromes in a w-bit window of the cyclic code in parallel; and detecting/locating error in the cyclic code based on the obtained syndromes. The decoding apparatus corresponds to the above method. And the corresponding decoder is also proposed in this invention. The method, apparatus and decoder according to the invention could process the cyclic code within a window width and thus enhance decoding efficiency in parallel.

Abstract: A switch of a data network implements both a bridge and a virtual bridge. In response to receipt of a data frame by the switch from an external link, the switch performs a lookup in a data structure using a source media access control (SMAC) address specified by the data frame. The switch determines if the external link is configured in a link aggregation group (LAG) and if the SMAC address is newly learned. In response to a determination that the external link is configured in a LAG and the SMAC address is newly learned, the switch associates the SMAC with the virtual bridge and communicates the association to a plurality of bridges in the data network.

Abstract: An information processing device, control method and program that suppresses security risks to a minimum. When power is activated, a control component starts by reading a first program from a first memory component and, in observance of the first memory program, it reads the identification information of an authentication device that is mounted to a mounting component, references a table T, and performs authentication processing for the authentication device, with the condition that the count value correspondingly listed for the identification information of the authentication device be larger than a prescribed value and, when authentication processing has succeeded, starts by reading the second program from a second memory component, and in the event that the authentication device continues to be mounted to the mounting component during executing the second program, decreases the table count value corresponding to the unique identification information of the authentication device.

Abstract: A cross system secure logon in a target system by using a first authentication system and a second authentication system. A correct password may be valid on the first authentication system and the second authentication system. An aspect includes receiving an input password, generating a first hash key by using the first authentication system, and/or generating a second hash key by using the second authentication system, wherein each authentication system uses a system unique non-collision free hash algorithm. Further, in one aspect, comparing the first hash key with a first predefined hash key of the correct password stored in the first authentication system, and/or comparing the second hash key with a second predefined hash key of the correct password stored in the second authentication system. Furthermore, granting access to the target system based on at least one of the comparisons.

Abstract: An adjustment apparatus includes a storage device, an execution target program, an execution unit, a first API, a second API, a profiler, and a dynamic compiler. The execution unit interprets the program, and calls and executes a function of an API in response to the API description. The first and second API are callable by the execution unit, to respectively allocate an array of a predetermined size, and extend the array. The first and second APIs are converted into code to store an array allocation call context of the pre-extension array into a profile information storage area of the allocated array. The profiler profiles access to arrays. The dynamic compiler inline-expands an array allocation call context included in a code part to be dynamically compiled and embeds an array size determined based on context based access information, as an allocation initial size of the array, into the code part.

Abstract: Methods, systems and products are provided relevant alert delivery including assigning by an event analyzer each received event to an events pool; determining by the event analyzer in dependence upon event analysis rules and the events assigned to the events pool whether to suppress one or more of the events; identifying by the event analyzer in dependence upon event analysis rules and the events assigned to the events pool one or more alerts; sending by the event analyzer to an alert analyzer all the alerts identified by the event analyzer; assigning by the alert analyzer the identified alerts to an alerts pool; determining by the alert analyzer in dependence upon alert analysis rules and the alerts in the alert pool whether to suppress any alerts; and transmitting the unsuppressed alerts to one or more components of the distributed processing system.

Abstract: The system of the present invention includes an instruction fetch unit 10, an instruction cache 20, a macro cache unit 30 for associating an instruction with one or more addresses in the main memory storing the instruction and holding the instruction and addresses, and a macro registration determining means 40 for holding instructions in the instruction cache 20 with a high cache hit frequency in the macro cache unit 30. The macro cache unit 30 associates the address specifying the instruction with an already held instruction and holds the address when the instruction specified for holding by the macro registration determining unit 40 is the same instruction already held, and associates the instruction with an address specifying the instruction and holds the instruction and the address when the instruction specified for holding by the macro registration determining unit 40 is not the same instruction being held.

Abstract: A system for automatically completing fields in online forms, such as login forms and new user registration forms, which employs a Master Cookie File containing sets of records associated with the user, his or her accounts or web sites, and registered values associated with form tags (e.g. username, password, address, email, telephone, etc.). When the user encounters another form, the MCF is automatically searched for matching values and form tags, primarily from the same account or web site, or alternatively from other accounts or sites. A flowing pop-up menu is displayed nearby the form fields from which the user can select values to automatically complete the form. Automatic account information updating, value expiration management, mapping of favorite values, and sharing of values are optional, enhanced functions of the invention.

Abstract: A point of sale interface (POS IF) emulator system includes a payment data processing-verification device that processes payment information in accordance with POS device information, emulates a POS input operation, and inputs the processed payment information to a POS device through a keyboard interface; the payment information being created from payment information extracted from shopping information and payment information acquired from user registration information, the shopping information being created by a mobile phone by acquiring item information from an item tag for an item and by performing the acquisition one or more times; wherein payment is made at the POS device corresponding to the POS device information.

Abstract: A mobile touch-generating device includes logic; a touch-generating system, including one or more touch-generating elements, operatively coupled to the logic and configured to generate touch events detectable by a touchscreen, via the elements; a network connectivity device operatively coupled to the logic to establish a secure connection with a server via a telecommunication network and receive data through an established secure connection; and a visualization device connectable to the logic to display contents according to data received through the established secure connection.

Abstract: Systems and methods to perform a register access are described. A particular method includes receiving a data frame at a bridge element of a plurality of bridge elements in communication with a plurality of server computers. The data frame may include a register access request and may be forwarded from a controlling bridge in communication with the plurality of bridge elements. A register may be accessed and execution of the register access request may be initiated in response to receiving the data frame.

Abstract: A method for data migration between storage devices according to an embodiment of the invention comprises: collecting an original time domain sequence of workload parameters of a data volume in a low speed storage device; evaluating a workload period of the data volume based on the collected original time domain sequence of the workload parameters; and migrating the data in the data volume according to the evaluated workload period so that the data is located in a high speed storage device during a workload peak of the data volume. The embodiments of the invention can improve a data access speed in the storage devices.

Abstract: A multi-addressable register file is addressed by a plurality of types of instructions, including scalar, vector and vector-scalar extension instructions. It may be determined that data is to be translated from one format to another format. If so determined, a convert machine instruction is executed that obtains a single precision datum in a first representation in a first format from a first register; converts the single precision datum of the first representation in the first format to a converted single precision datum of a second representation in a second format; and places the converted single precision datum in a second register.

Abstract: A relocation mechanism in a multi-nodal computer environment dynamically routes processing units in a distributed computer system based on incoming physical data into the processing unit. The relocation mechanism makes an initial location decision to place a processing unit onto a node in the distributed computer system. The relocation mechanism monitors physical data flowing into a processing unit or node and dynamically relocates the processing unit to another type of node within the ‘cloud’ of nodes based on the type of physical data or pattern of data flowing into the processing unit. The relocation mechanism may use one or more rules with criteria for different data types observed in the data flow to optimize when to relocate the processing units.

Abstract: A method and apparatus for transferring architected state bypasses system memory by directly transmitting architected state between processor cores over a dedicated interconnect. The transfer may be performed by state transfer interface circuitry with or without software interaction. The architected state for a thread may be transferred from a first processing core to a second processing core when the state transfer interface circuitry detects an error that prevents proper execution of the thread corresponding to the architected state. A program instruction may be used to initiate the transfer of the architected state for the thread to one or more other threads in order to parallelize execution of the thread or perform load balancing between multiple processor cores by distributing processing of multiple threads.

Abstract: Administering incident pools including creating a pool of incidents, the pool having a predetermined initial period of time; assigning each received incident to the pool; assigning, by the incident analyzer, to each incident a predetermined minimum time for inclusion in a pool; extending for one or more of the incidents the predetermined initial period of time of the pool by a particular period of time assigned to the incident; determining whether conditions have been met to close the pool; and if conditions have been met to close the pool determining for each incident in the pool whether the incident has been in the pool for its predetermined minimum time for inclusion in a pool; and if the incident has not been in the pool for its predetermined minimum time, evicting the incident from the closed pool and including the incident in a next pool.