Abstract: A multi-phase DC-to-DC controller is provided. The controller includes a plurality of current sense circuits that sense current in respective converter cell of the converter, and generate respective current sense signals, an averaging circuit that receives the respective current sense signals and generates an average signal, a plurality of error detector circuits that compare respective current sense signals with the average signal and generate respective voltage imbalance signals, a plurality of transconductor circuits that convert respective voltage imbalance signals to respective current imbalance signals, and a plurality of pulse width modulation (PWM) generators that output PWM signals to control respective converter cells based on a comparison between a ramp threshold voltage of the PWM generators and a PWM ramp voltage that is based on the sum of one of the respective current imbalance signals and a first current that is proportional to the input voltage.

Abstract: According to an aspect of one or more exemplary embodiments, there is provided a constant on-time buck converter with calibrated ripple injection having improved light load transient response and reduced output capacitor size.

Abstract: According to an aspect of one or more exemplary embodiments, there is provided a constant on-time controller for a buck converter with calibrated ripple injection in continuous conduction mode. The constant on-time controller may include a pulse width modulator (PWM) comparator that generates an on-time request, an error amplifier that regulates an average feedback voltage to an internal reference voltage, and passes a feedback node ripple signal to an input of the PWM comparator, an on-time generator that outputs an on-time signal that controls an on-time of the buck converter based on the on-time request, a MOSFET driver that drives the buck converter based on the output of the on-time generator, and an injection signal generator coupled to the on-time generator, wherein the injection signal generator may include a first switch and a second switch, a fixed signal generator, and a bias current source.

Abstract: A multiple-phase parallelable constant on time (COT) buck controller, a first phase containing a first memory bit and a second phase containing a second memory bit. The COT buck controller includes a first converter comprising a first constant TON generator configured to sense and deliver a first TON request when the first memory bit is in a logic one state, and a second converter connected in parallel with the first converter, the second converter comprising a second constant TON generator configured to sense and deliver a second TON request when the second memory bit is in the logic one state, only one of the first memory bit and the second memory bit being in the logic one state thus generating activity in a daisy chain ring where each of the first converter and the second converter senses and delivers a corresponding TON request in a sequential manner.

Abstract: A multiple-phase parallelable constant on time (COT) buck controller, a first phase containing a first memory bit and a second phase containing a second memory bit. The COT buck controller includes a first converter comprising a first constant TON generator configured to sense and deliver a first TON request when the first memory bit is in a logic one state, and a second converter connected in parallel with the first converter, the second converter comprising a second constant TON generator configured to sense and deliver a second TON request when the second memory bit is in the logic one state, only one of the first memory bit and the second memory bit being in the logic one state thus generating activity in a daisy chain ring where each of the first converter and the second converter senses and delivers a corresponding TON request in a sequential manner.

Abstract: A multi-phase DC-to-DC buck converter for receiving an input voltage and delivering an output voltage to a load by splitting the load current between a plurality of DC-to-DC buck converter cells. The converter includes a plurality of current sense circuits for sensing current in a respective converter cell, each of the current sense circuits configured to generate a respective current sense signal, an averaging circuit for receiving each of the respective current sense signals and generating an average signal, a plurality of imbalance detector circuits for comparing a respective current sense signal with the average signal and generating a respective current imbalance signal, and a plurality of ON time generators for activating a converter cell for a predetermined time interval and altering the predetermined time interval in accordance with a time integral of a respective current imbalance signal.

Abstract: A switching regulator using current mode control and adaptive slope compensation includes a DC correction circuit to introduce a DC correction signal to cancel the DC offset error generated by the slope compensation signal. In some embodiments, the DC correction signal is a function of the input voltage and the output voltage and is applied in response to the slope compensation signal being applied. In one embodiment, the DC correction signal is a linear function of the input voltage and the output voltage.

Abstract: A switching regulator using current mode control and adaptive slope compensation includes a DC correction circuit to introduce a DC correction signal to cancel the DC offset error generated by the slope compensation signal. In some embodiments, the DC correction signal is a function of the input voltage and the output voltage and is applied in response to the slope compensation signal being applied. In one embodiment, the DC correction signal is a linear function of the input voltage and the output voltage.

Abstract: A buck switching regulator formed on an integrated circuit receives an input voltage and provides a switching output voltage on a switch output node using a constant on-time, variable off-time feedback control loop. The buck switching regulator includes an amplifier comparing a feedback voltage to a reference voltage and generating an output voltage on an output terminal, a first capacitor and a first resistor connected in series between the switch output node and the output terminal of the amplifier, and a second capacitor coupled between the DC output voltage node and the output terminal of the amplifier. The first capacitor and the first resistor generate a ripple voltage signal which is injected onto the output terminal of the amplifier for use in the constant on-time, variable off-time feedback control scheme. The magnitude of the ripple voltage signal is a function of the capacitance value of the second capacitor.

Abstract: A buck switching regulator formed on an integrated circuit and receives an input voltage and provides a switching output voltage on a switch output node using a fixed on-time, minimum off-time feedback control scheme. The buck switching regulator includes a first capacitor and a first resistor formed on the integrated circuit where the first capacitor and the first resistor are connected in series between the switch output node and a feedback voltage node, and a second capacitor coupled between the DC output voltage node and the feedback voltage node. The first capacitor and the first resistor generate a ripple voltage signal being related to the switching output voltage and provide the ripple voltage signal to the feedback voltage node for use in the fixed on-time, minimum off-time feedback control scheme where the magnitude of the ripple voltage signal is a function of the capacitance value of the second capacitor.

Abstract: An analog soft-start circuit for a switching regulator (e.g., a buck converter) including an analog ramp circuit and an open-loop analog voltage clamp circuit. The voltage ramp circuit utilizes a two-stage current divider circuit to generate a very low, stable current signal, and an integrator circuit including a relatively small, integral capacitor to generate the ramp voltage signal in response to the very low current signal. The analog voltage clamp circuit clamps the regulated output signal to the ramp voltage until the ramp voltage signal increases to a predetermined voltage level, thereby causing the regulated output voltage to exhibit the desired soft-start characteristics. The analog clamp circuit includes a current mirror circuit that generates a clamp current that pulls down the error amplifier output stage via a clamping element (e.g., a diode) until the ramp voltage signal reaches a predetermined level.

Abstract: A buck switching regulator formed on an integrated circuit receives an input voltage and provides a switching output voltage on a switch output node using a constant on-time, variable off-time feedback control loop. The buck switching regulator includes an amplifier comparing a feedback voltage to a reference voltage and generating an output voltage on an output terminal, a first capacitor and a first resistor connected in series between the switch output node and the output terminal of the amplifier, and a second capacitor coupled between the DC output voltage node and the output terminal of the amplifier. The first capacitor and the first resistor generate a ripple voltage signal which is injected onto the output terminal of the amplifier for use in the constant on-time, variable off-time feedback control scheme. The magnitude of the ripple voltage signal is a function of the capacitance value of the second capacitor.

Abstract: A buck switching regulator formed on an integrated circuit and receives an input voltage and provides a switching output voltage on a switch output node using a fixed on-time, minimum off-time feedback control scheme. The buck switching regulator includes a first capacitor and a first resistor formed on the integrated circuit where the first capacitor and the first resistor are connected in series between the switch output node and a feedback voltage node, and a second capacitor coupled between the DC output voltage node and the feedback voltage node. The first capacitor and the first resistor generate a ripple voltage signal being related to the switching output voltage and provide the ripple voltage signal to the feedback voltage node for use in the fixed on-time, minimum off-time feedback control scheme where the magnitude of the ripple voltage signal is a function of the capacitance value of the second capacitor.

Abstract: An analog soft-start circuit for a switching regulator (e.g., a buck converter) including an analog ramp circuit and an open-loop analog voltage clamp circuit. The voltage ramp circuit utilizes a two-stage current divider circuit to generate a very low, stable current signal, and an integrator circuit including a relatively small, integral capacitor to generate the ramp voltage signal in response to the very low current signal. The analog voltage clamp circuit clamps the regulated output signal to the ramp voltage until the ramp voltage signal increases to a predetermined voltage level, thereby causing the regulated output voltage to exhibit the desired soft-start characteristics. The analog clamp circuit includes a current mirror circuit that generates a clamp current that pulls down the error amplifier output stage via a clamping element (e.g., a diode) until the ramp voltage signal reaches a predetermined level.

Abstract: A dual mode regulator, having a high current PWM regulator mode and a low current LDO regulator mode, briefly changes the operating parameters of the PWM and LDO regulators during a transition between modes. Changes during the transition period include: raising the error amplifier reference voltage of the LDO or PWM regulator to ensure a definite handover, raising the bias current in the LDO stages during the transition to cause the LDO regulator to quickly and stably respond to voltage glitches, and augmenting the LDO regulator series pass transistors with one or more additional pass transistors during the transition to enable the LDO regulator to handle higher currents. After the transition, the operating parameters of the enabled regulator portion are reset to their nominal values. The PWM regulator is started with a soft start routine to limit current through the power transistor.

Abstract: A dual mode regulator, having a high current PWM regulator mode and a low current LDO regulator mode, briefly changes the operating parameters of the PWM and LDO regulators during a transition between modes. Changes during the transition period include: raising the error amplifier reference voltage of the LDO or PWM regulator to ensure a definite handover, raising the bias current in the LDO stages during the transition to cause the LDO regulator to quickly and stably respond to voltage glitches, and augmenting the LDO regulator series pass transistors with one or more additional pass transistors during the transition to enable the LDO regulator to handle higher currents. After the transition, the operating parameters of the enabled regulator portion are reset to their nominal values. The PWM regulator is started with a soft start routine to limit current through the power transistor.

Abstract: A semiconductor integrated circuit to provide a low distortion, large swing intermediate frequency wherein the circuit includes the function of mixing, filtering, and amplification on a single chip. A pair of differential currents are obtained from the mixer, the differential currents are filtered and conditioned, converted to a pair of differential voltages and amplified to obtain the low distortion, large swing intermediate frequency.