Abstract: Embodiments of this disclosure include methods in which spurs generated by the drifting of an oscillation frequency of an oscillation signal provided by a free-running oscillator may be minimized and/or eliminated from an output signal of a phase locked loop (PLL). Methods include minimizing the mixing gain between the oscillation signal and a power signal provided to the PLL. The oscillation signal and the power signal may be mixed in a phase frequency detector (PFD) included in the PLL. The minimizing of the mixing gain for the PFD also minimizes the degrading effect that the spurs have on the overall performance of the communications device. The mixing gain may be minimized by minimizing the impedance provided at nodes included in the PFD where the oscillation signal and the power signal mix. The mixing gain may also be minimized by maximizing the power supply rejection ratio for the PFD.

Abstract: Embodiments of this disclosure include methods in which spurs generated by the drifting of an oscillation frequency of an oscillation signal provided by a free-running oscillator may be minimized and/or eliminated from an output signal of a phase locked loop (PLL). Methods include minimizing the mixing gain between the oscillation signal and a power signal provided to the PLL. The oscillation signal and the power signal may be mixed in a phase frequency detector (PFD) included in the PLL. The minimizing of the mixing gain for the PFD also minimizes the degrading effect that the spurs have on the overall performance of the communications device. The mixing gain may be minimized by minimizing the impedance provided at nodes included in the PFD where the oscillation signal and the power signal mix. The mixing gain may also be minimized by maximizing the power supply rejection ratio for the PFD.

Abstract: Methods and systems for coexistence in a multiband, multistandard communication system utilizing a plurality of phase locked loops (PLLs) are disclosed. Aspects may include determining one or more desired frequencies of operation of a transceiver, determining a frequency of unwanted signals such as spurs, intermodulation, and/or mixing product signals, and configuring the Plls to operate at a multiple of the desired frequencies while avoiding the unwanted signals. The desired frequencies may be generated utilizing integer, which may include multi-modulus dividers. The wireless standards may include LTE, GSM, EDGE, GPS, Bluetooth, WiFi, and/or WCOMA, for example. The frequencies may be configured to mitigate interference. Plls may be shared when operating in TOO mode, and used separately operating in FOO mode. One or more digital interface signals, zero exceptions on a transmitter spur emission mask, and sampling clocks for AOCs and/or DACs in the transceiver may be generated utilizing the PLLs.

Abstract: Embodiments of this disclosure include methods in which spurs generated by the drifting of an oscillation frequency of an oscillation signal provided by a free-running oscillator may be minimized and/or eliminated from an output signal of a phase locked loop (PLL). Methods include minimizing the mixing gain between the oscillation signal and a power signal provided to the PLL. The oscillation signal and the power signal may be mixed in a phase frequency detector (PFD) included in the PLL. The minimizing of the mixing gain for the PFD also minimizes the degrading effect that the spurs have on the overall performance of the communications device. The mixing gain may be minimized by minimizing the impedance provided at nodes included in the PFD where the oscillation signal and the power signal mix. The mixing gain may also be minimized by maximizing the power supply rejection ratio for the PFD.

Abstract: An integrated circuit assembly is provided that includes an integrated circuit (IC) package substrate including a package ground rail that is divided into a plurality of segments that are electrically isolated from each other. An IC die is disposed on the IC package substrate, the IC die including a plurality of circuit blocks and an IC ground rail. The IC ground rail is divided into a plurality of segments, where each segment of the IC ground rail is coupled to another segment of the IC ground rail by one or more diodes. The plurality of circuit blocks have corresponding ground nodes electrically connected to corresponding segments of the IC ground rail. The segments of the IC ground rail are electrically coupled to corresponding segments of the package ground rail by corresponding first connections.

Abstract: Embodiments of this disclosure include methods in which spurs generated by the drifting of an oscillation frequency of an oscillation signal provided by a free-running oscillator may be minimized and/or eliminated from an output signal of a phase locked loop (PLL). Methods include minimizing the mixing gain between the oscillation signal and a power signal provided to the PLL. The oscillation signal and the power signal may be mixed in a phase frequency detector (PFD) included in the PLL. The minimizing of the mixing gain for the PFD also minimizes the degrading effect that the spurs have on the overall performance of the communications device. The mixing gain may be minimized by minimizing the impedance provided at nodes included in the PFD where the oscillation signal and the power signal mix. The mixing gain may also be minimized by maximizing the power supply rejection ratio for the PFD.

Abstract: An integrated circuit assembly is provided that includes an integrated circuit (IC) package substrate including a package ground rail that is divided into a plurality of segments that are electrically isolated from each other. An IC die is disposed on the IC package substrate, the IC die including a plurality of circuit blocks and an IC ground rail. The IC ground rail is divided into a plurality of segments, where each segment of the IC ground rail is coupled to another segment of the IC ground rail by one or more diodes. The plurality of circuit blocks have corresponding ground nodes electrically connected to corresponding segments of the IC ground rail. The segments of the IC ground rail are electrically coupled to corresponding segments of the package ground rail by corresponding first connections.

Abstract: Methods and systems for coexistence in a multiband, multistandard communication system utilizing a plurality of phase locked loops (PLLs) are disclosed. Aspects may include determining one or more desired frequencies of operation of a transceiver, determining a frequency of unwanted signals such as spurs, intermodulation, and/or mixing product signals, and configuring the Plls to operate at a multiple of the desired frequencies while avoiding the unwanted signals. The desired frequencies may be generated utilizing integer, which may include multi-modulus dividers. The wireless standards may include LTE, GSM, EDGE, GPS, Bluetooth, WiFi, and/or WCOMA, for example. The frequencies may be configured to mitigate interference. Plls may be shared when operating in TOO mode, and used separately operating in FOO mode. One or more digital interface signals, zero exceptions on a transmitter spur emission mask, and sampling clocks for AOCs and/or DACs in the transceiver may be generated utilizing the PLLs.

Abstract: Methods and systems for coexistence in a multiband, multistandard communication system utilizing a plurality of phase locked loops (PLLs) are disclosed. Aspects may include determining one or more desired frequencies of operation of a transceiver, determining a frequency of unwanted signals such as spurs, intermodulation, and/or mixing product signals, and configuring the PLLs to operate at a multiple of the desired frequencies while avoiding the unwanted signals. The desired frequencies may be generated utilizing integer, which may include multi-modulus dividers. The wireless standards may include LTE, GSM, EDGE, GPS, Bluetooth, WiFi, and/or WCDMA, for example. The frequencies may be configured to mitigate interference. PLLs may be shared when operating in TDD mode, and used separately operating in FDD mode. One or more digital interface signals, zero exceptions on a transmitter spur emission mask, and sampling clocks for ADCs and/or DACs in the transceiver may be generated utilizing the PLLs.

Abstract: Methods and systems for coexistence in a multiband, multistandard communication system utilizing a plurality of phase locked loops (PLLs) are disclosed. Aspects may include determining one or more desired frequencies of operation of a transceiver, determining a frequency of unwanted signals such as spurs, intermodulation, and/or mixing product signals, and configuring the PLLs to operate at a multiple of the desired frequencies while avoiding the unwanted signals. The desired frequencies may be generated utilizing integer, which may include multi-modulus dividers. The wireless standards may include LTE, GSM, EDGE, GPS, Bluetooth, WiFi, and/or WCDMA, for example. The frequencies may be configured to mitigate interference. PLLs may be shared when operating in TDD mode, and used separately operating in FDD mode. One or more digital interface signals, zero exceptions on a transmitter spur emission mask, and sampling clocks for ADCs and/or DACs in the transceiver may be generated utilizing the PLLs.

Abstract: Methods and systems for coexistence in a multiband, multistandard communication system utilizing a plurality of phase locked loops (PLLs) are disclosed. Aspects may include determining one or more desired frequencies of operation of a transceiver, determining a frequency of unwanted signals such as spurs, intermodulation, and/or mixing product signals, and configuring the PLLs to operate at a multiple of the desired frequencies while avoiding the unwanted signals. The desired frequencies may be generated utilizing integer, which may include multi-modulus dividers. The wireless standards may include LTE, GSM, EDGE, GPS, Bluetooth, WiFi, and/or WCDMA, for example. The frequencies may be configured to mitigate interference. PLLs may be shared when operating in TDD mode, and used separately operating in FDD mode. One or more digital interface signals, zero exceptions on a transmitter spur emission mask, and sampling clocks for ADCs and/or DACs in the transceiver may be generated utilizing the PLLs.

Abstract: Methods and systems for coexistence in a multiband, multistandard communication system utilizing a plurality of phase locked loops (PLLs) are disclosed. Aspects may include determining one or more desired frequencies of operation of a transceiver, determining a frequency of unwanted signals such as spurs, intermodulation, and/or mixing product signals, and configuring the PLLs to operate at a multiple of the desired frequencies while avoiding the unwanted signals. The desired frequencies may be generated utilizing integer, which may include multi-modulus dividers. The wireless standards may include LTE, GSM, EDGE, GPS, Bluetooth, WiFi, and/or WCDMA, for example. The frequencies may be configured to mitigate interference. PLLs may be shared when operating in TDD mode, and used separately operating in FDD mode. One or more digital interface signals, zero exceptions on a transmitter spur emission mask, and sampling clocks for ADCs and/or DACs in the transceiver may be generated utilizing the PLLs.

Abstract: Aspects of a method and system for a multi-band direct conversion CMOS mobile television tuner are provided. A single-chip multi-band RF receiver in a mobile terminal comprising UHF and L-band front-ends receives and amplifies an RF signal utilizing an LNA integrated into the front-end that corresponds to the type of signal received. A received signal strength indicator (RSSI) value may be determined for the amplified signal within the single-chip receiver and may be utilized to adjust a gain of the LNA. The adjustment may be made via on-chip or off-chip processing of the RSSI value. The single-chip receiver may directly convert the amplified signal to a baseband frequency signal and generate in-phase and quadrature components. The components of the baseband frequency signal may be filtered and/or amplified via programmable devices within the single-chip receiver. Circuitry within the single-chip receiver may be controller via an on-chip digital interface.

Abstract: Aspects of a method and system for a fractional-N synthesizer for a mobile digital cellular television environment are presented. Aspects of the system may include circuitry, within a phase locked loop, that enables determination of a division number at a time instant within a division cycle. A local oscillator signal may be modified based on the division number in a succeeding division cycle. A subsequent local oscillator signal may be generated based on the modification.

Abstract: A current steering charge pump that receives control signals and sources and sinks current in response to the control signals. One embodiment includes a main current source, secondary current source, main current sink, and secondary current sink, and three different current paths between various of the current sources and current sinks. One embodiment includes buffers operative to maintain the node voltages of central nodes at the same voltage as the output node of the charge pump, where each buffer is coupled between two of the three current paths.