Patents by Inventor Ippei Kume
Ippei Kume has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11769747Abstract: In one embodiment, a semiconductor device includes a first insulator. The device further includes a first pad provided in the first insulator, and including first and second layers provided on lateral and lower faces of the first insulator in order. The device further includes a second insulator provided on the first insulator. The device further includes a second pad provided on the first pad in the second insulator, and including third and fourth layers provided on lateral and upper faces of the second insulator in order. The device further includes a first portion provided between an upper face of the first pad and a lower face of the second insulator or between a lower face of the second pad and an upper face of the first insulator, and including a metal element same as a metal element included in the first layer or the third layer.Type: GrantFiled: June 17, 2021Date of Patent: September 26, 2023Assignee: Kioxia CorporationInventors: Genki Sawada, Masayoshi Tagami, Jun Iijima, Ippei Kume, Kiyomitsu Yoshida
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Publication number: 20230088551Abstract: According to one embodiment, a semiconductor memory device includes: a first chip including first conductive layers arranged at intervals in a first direction, a first semiconductor layer extending through an inside of the first conductive layers in the first direction, a first insulating film between the first semiconductor layer and the first conductive layers, a second semiconductor layer provided above the first conductive layers and in contact with the first semiconductor layer, and a first electrode provided in contact with an upper side of the second semiconductor layer; and a second chip including a second electrode in contact with the first electrode, and a second conductive layer in contact with the second electrode.Type: ApplicationFiled: March 4, 2022Publication date: March 23, 2023Inventor: Ippei KUME
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Patent number: 11587849Abstract: A device includes a substrate having a first-face and a second-face. An electrode is provided in a through hole that penetrates through the substrate between the first-face and the second-face. A first-insulator is provided in the substrate and protrudes in a radial direction from an opening end of the through hole on a side close to the second-face to a center of the through hole as viewed from above the first-face. A second-insulator protrudes in the radial direction from the first-insulator as viewed from above the first-face, is thinner than the first-insulator, and is in contact with the electrode. A third-insulator is provided between an inner wall of the through hole and the electrode, and includes a first-portion that is in contact with the first-insulator and a second-portion that is in contact with the inner wall of the through hole and is closer to the second-face than the first-portion.Type: GrantFiled: December 9, 2020Date of Patent: February 21, 2023Assignee: Kioxia CorporationInventors: Ippei Kume, Kazuhiko Nakamura, Shinya Okuda
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Publication number: 20220189905Abstract: In one embodiment, a semiconductor device includes a first insulator. The device further includes a first pad provided in the first insulator, and including first and second layers provided on lateral and lower faces of the first insulator in order. The device further includes a second insulator provided on the first insulator. The device further includes a second pad provided on the first pad in the second insulator, and including third and fourth layers provided on lateral and upper faces of the second insulator in order. The device further includes a first portion provided between an upper face of the first pad and a lower face of the second insulator or between a lower face of the second pad and an upper face of the first insulator, and including a metal element same as a metal element included in the first layer or the third layer.Type: ApplicationFiled: June 17, 2021Publication date: June 16, 2022Applicant: Kioxia CorporationInventors: Genki SAWADA, Masayoshi TAGAMI, Jun IIJIMA, Ippei KUME, Kiyomitsu YOSHIDA
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Publication number: 20220084907Abstract: A device includes a substrate having a first-face and a second-face. An electrode is provided in a through hole that penetrates through the substrate between the first-face and the second-face. A first-insulator is provided in the substrate and protrudes in a radial direction from an opening end of the through hole on a side close to the second-face to a center of the through hole as viewed from above the first-face. A second-insulator protrudes in the radial direction from the first-insulator as viewed from above the first-face, is thinner than the first-insulator, and is in contact with the electrode. A third-insulator is provided between an inner wall of the through hole and the electrode, and includes a first-portion that is in contact with the first-insulator and a second-portion that is in contact with the inner wall of the through hole and is closer to the second-face than the first-portion.Type: ApplicationFiled: December 9, 2020Publication date: March 17, 2022Applicant: Kioxia CorporationInventors: Ippei KUME, Kazuhiko NAKAMURA, Shinya OKUDA
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Patent number: 11139208Abstract: A semiconductor device includes a semiconductor wafer chip, a semiconductor device layer, and a reflectance reducing layer. The semiconductor wafer chip includes a device region and a peripheral region around the device region. The peripheral region includes a plurality of voids aligned along a side surface of the semiconductor wafer chip at a predetermined depth from a first surface of the semiconductor wafer chip. The semiconductor device element layer is on the first surface in the device region. The reflectance reducing layer is on the first surface of the semiconductor wafer chip in the peripheral region, that reduces a reflection of laser light incident from a second surface of the semiconductor wafer chip.Type: GrantFiled: September 3, 2019Date of Patent: October 5, 2021Assignee: TOSHIBA MEMORY CORPORATIONInventors: Takanobu Ono, Tsutomu Fujita, Ippei Kume, Akira Tomono
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Patent number: 11043419Abstract: A semiconductor device according to an embodiment comprises a semiconductor substrate having a through hole from a first face to a second face on an opposite side to the first face. A metal part is provided inside the through hole. A stacked film is provided between the metal part and an inner side surface of the through hole, and comprises a plurality of different material films of two or more types having a relative permittivity equal to or lower than 6.5.Type: GrantFiled: March 6, 2019Date of Patent: June 22, 2021Assignee: TOSHIBA MEMORY CORPORATIONInventor: Ippei Kume
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Patent number: 10971400Abstract: A semiconductor device includes a device layer having a semiconductor element and a wiring layer, a first structure, a second structure at an outer periphery of the first structure and having a thickness smaller than that of the first structure, and a conductive layer that covers the first structure and the second structure. The first structure comprises a first substrate having the device layer formed on a first surface thereof and a through hole formed through a second surface thereof that is opposite to the first surface to reach the device layer, and an inner portion of a second substrate facing the first surface and bonded to the first surface by a first adhesive layer.Type: GrantFiled: September 2, 2019Date of Patent: April 6, 2021Assignee: TOSHIBA MEMORY CORPORATIONInventors: Masahiko Murano, Fumito Shoji, Tatsuo Migita, Ippei Kume
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Patent number: 10943852Abstract: According to some embodiments, a semiconductor device includes a semiconductor substrate, a metal portion, a first insulating film, and a second insulating film. The semiconductor substrate has a through-hole extending from a first surface of the semiconductor substrate to a second surface thereof opposite to the first surface. The metal portion is formed in the through-hole. The first insulating film is provided on the second surface of the semiconductor substrate and on a side surface of the through-hole. The second insulating film has a dielectric constant of not more than 6.5 and is provided on a metal portion-side surface of the first insulating film on the side surface of the through-hole of the semiconductor substrate.Type: GrantFiled: February 26, 2019Date of Patent: March 9, 2021Assignee: TOSHIBA MEMORY CORPORATIONInventors: Ippei Kume, Taketo Matsuda, Shinya Okuda, Masahiko Murano
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Patent number: 10892232Abstract: A semiconductor device according to an embodiment includes a semiconductor substrate comprising a first face, and a second face on an opposite side to the first face. A semiconductor element is provided on the first face of the semiconductor substrate. A polycrystalline or non-crystalline first material layer is provided at least on an outer edge of the first face of the semiconductor substrate. A second material layer is provided on the second face of the semiconductor substrate. The second material layer transmits laser light.Type: GrantFiled: September 3, 2019Date of Patent: January 12, 2021Assignee: Toshiba Memory CorporationInventors: Takanobu Ono, Tsutomu Fujita, Ippei Kume, Akira Tomono
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Patent number: 10804152Abstract: According to one embodiment, a method of manufacturing a semiconductor device includes: bonding a first surface of a device substrate on which a device is formed on a first surface to a support substrate via an adhesive; after bonding the device substrate to the support substrate, grinding and thinning a second surface side opposite to the first surface of the device substrate based on an in-plane processing rate at the time of forming a semiconductor substrate by RIE; after thinning the device substrate, forming a hole penetrating the device substrate by RIE; and burying metal in the hole to forma through electrode.Type: GrantFiled: February 11, 2019Date of Patent: October 13, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Masaya Shima, Ippei Kume, Eiichi Shin, Eiji Takano, Takashi Shirono, Mika Fujii
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Publication number: 20200294934Abstract: A semiconductor device according to an embodiment includes a semiconductor substrate comprising a first face, and a second face on an opposite side to the first face. A semiconductor element is provided on the first face of the semiconductor substrate. A polycrystalline or non-crystalline first material layer is provided at least on an outer edge of the first face of the semiconductor substrate. A second material layer is provided on the second face of the semiconductor substrate. The second material layer transmits laser light.Type: ApplicationFiled: September 3, 2019Publication date: September 17, 2020Applicant: Toshiba Memory CorporationInventors: Takanobu ONO, Tsutomu FUJITA, Ippei KUME, Akira TOMONO
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Publication number: 20200294856Abstract: A semiconductor device includes a semiconductor wafer chip, a semiconductor device layer, and a reflectance reducing layer. The semiconductor wafer chip includes a device region and a peripheral region around the device region. The peripheral region includes a plurality of voids aligned along a side surface of the semiconductor wafer chip at a predetermined depth from a first surface of the semiconductor wafer chip. The semiconductor device element layer is on the first surface in the device region. The reflectance reducing layer is on the first surface of the semiconductor wafer chip in the peripheral region, that reduces a reflection of laser light incident from a second surface of the semiconductor wafer chip.Type: ApplicationFiled: September 3, 2019Publication date: September 17, 2020Inventors: Takanobu ONO, Tsutomu FUJITA, Ippei KUME, Akira TOMONO
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Publication number: 20200273749Abstract: A semiconductor device includes a device layer having a semiconductor element and a wiring layer, a first structure, a second structure at an outer periphery of the first structure and having a thickness smaller than that of the first structure, and a conductive layer that covers the first structure and the second structure. The first structure comprises a first substrate having the device layer formed on a first surface thereof and a through hole formed through a second surface thereof that is opposite to the first surface to reach the device layer, and an inner portion of a second substrate facing the first surface and bonded to the first surface by a first adhesive layer.Type: ApplicationFiled: September 2, 2019Publication date: August 27, 2020Inventors: Masahiko MURANO, Fumito SHOJI, Tatsuo MIGITA, Ippei KUME
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Patent number: 10741505Abstract: A method of manufacturing a semiconductor device includes stacking a first substrate comprising a first surface having a semiconductor element and an opposing second surface and a second substrate comprising a third surface having a semiconductor element and an opposing fourth surface, forming a first contact hole extending from the second surface to the first surface of the first substrate and forming a first groove inwardly of a first region of the second surface of the first substrate by etching inwardly of the first substrate from the second surface thereof, forming a first patterned mask on the first substrate, so that the first groove is covered by the material of the first patterned mask, forming a first metal electrode in the first contact hole through an opening in the first mask as a mask, and removing the first mask and subsequently cutting through the first substrate in the first groove.Type: GrantFiled: January 7, 2019Date of Patent: August 11, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Masaya Shima, Eiji Takano, Ippei Kume, Yuki Noda
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Publication number: 20200075498Abstract: A semiconductor device according to an embodiment comprises a semiconductor substrate having a through hole from a first face to a second face on an opposite side to the first face. A metal part is provided inside the through hole. A stacked film is provided between the metal part and an inner side surface of the through hole, and comprises a plurality of different material films of two or more types having a relative permittivity equal to or lower than 6.5.Type: ApplicationFiled: March 6, 2019Publication date: March 5, 2020Applicant: TOSHIBA MEMORY CORPORATIONInventor: Ippei KUME
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Patent number: 10566311Abstract: A semiconductor device includes a first and a second chips. A first inductor is above a first surface or a second surface located on an opposite side to the first surface. A first metal electrode is between the first and second surface to penetrate through the first substrate and to be connected to the first inductor. The second chip includes a second element provided on a third surface of a second substrate. A second inductor provided above a third surface of the second substrate or a fourth surface located on an opposite side to the third surface. A second metal electrode is provided between the third surface and the fourth surface to penetrate through the second substrate and to be connected to the second inductor. The first and second chips are stacked. The first and second inductors are electrically connected via the first or second metal electrode, as one inductor.Type: GrantFiled: September 12, 2017Date of Patent: February 18, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventor: Ippei Kume
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Publication number: 20190363037Abstract: According to some embodiments, a semiconductor device includes a semiconductor substrate, a metal portion, a first insulating film, and a second insulating film. The semiconductor substrate has a through-hole extending from a first surface of the semiconductor substrate to a second surface thereof opposite to the first surface. The metal portion is formed in the through-hole. The first insulating film is provided on the second surface of the semiconductor substrate and on a side surface of the through-hole. The second insulating film has a dielectric constant of not more than 6.5 and is provided on a metal portion-side surface of the first insulating film on the side surface of the through-hole of the semiconductor substrate.Type: ApplicationFiled: February 26, 2019Publication date: November 28, 2019Applicant: TOSHIBA MEMORY CORPORATIONInventors: Ippei Kume, Taketo Matsuda, Shinya Okuda, Masahiko Murano
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Publication number: 20190348324Abstract: According to one embodiment, a method of manufacturing a semiconductor device includes: bonding a first surface of a device substrate on which a device is formed on a first surface to a support substrate via an adhesive; after bonding the device substrate to the support substrate, grinding and thinning a second surface side opposite to the first surface of the device substrate based on an in-plane processing rate at the time of forming a semiconductor substrate by RIE; after thinning the device substrate, forming a hole penetrating the device substrate by RIE; and burying metal in the hole to forma through electrode.Type: ApplicationFiled: February 11, 2019Publication date: November 14, 2019Applicant: Toshiba Memory CorporationInventors: Masaya SHIMA, Ippei KUME, Eiichi SHIN, Eiji TAKANO, Takashi SHIRONO, Mika FUJII
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Patent number: 10468334Abstract: A semiconductor device according to an embodiment includes a semiconductor substrate including a first face having semiconductor elements, and a second face on an opposite side to the first face. A first insulating film is located on the first face of the semiconductor substrate. A conductor is located on the first insulating film. A metal electrode is located between the first face and the second face and passes through the semiconductor substrate to be in contact with the conductor. A second insulating film is located between the metal electrode and the semiconductor substrate. A boundary face between the first insulating film and the second insulating film is located on a side of the conductor relative to the first face of the semiconductor substrate and is inclined to approach the conductor toward a center portion of the metal electrode.Type: GrantFiled: September 12, 2017Date of Patent: November 5, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventors: Ippei Kume, Kazuhiko Nakamura, Yuki Noda