Abstract: Structures and methods are provided for integrating a resistance random access memory (ReRAM) in a back-end-on-the-line (BEOL) fat wire level. In one embodiment, a ReRAM device area contact structure is provided in the BEOL fat wire level that has at least a lower via portion that contacts a surface of a top electrode of a ReRAM device area ReRAM-containing stack. In other embodiments, a tall ReRAM device area bottom electrode is provided in the BEOL fat wire level and embedded in a dielectric material stack that includes a dielectric capping layer and an interlayer dielectric material layer.

Abstract: A phase change memory (PCM) cell includes an electrode, a heater electrically connected to the electrode, a PCM material electrically connected to the heater, a second electrode electrically connected to the PCM material, an electrical insulator surrounding the PCM material, and a shield positioned between the PCM material and the electrical insulator, the shield comprising a reactive-ion-etching-resistant material.

Abstract: A phase change memory structure including a bottom electrode; a top electrode; a first phase change material between the bottom electrode and the top electrode; a first dielectric surrounding the first phase change material; a second dielectric surrounding the top electrode, the second dielectric having selective adhesion to a metal as compared to the first phase change material; a first metal feature contacting the bottom electrode; and a second metal feature contacting the top electrode.

Abstract: An apparatus includes a heater, a phase change material region, and a top metal layer. The phase change material region includes a doped GST layer and a first GST layer. The first GST layer is between the doped GST layer and the heater, and the doped GST layer is doped differently than the first GST layer. The phase change material region is positioned between the heater and the top metal layer.

Abstract: Structures and methods are provided for integrating a resistance random access memory (ReRAM) in a back-end-on-the-line (BEOL) fat wire level. In one embodiment, a ReRAM device area contact structure is provided in the BEOL fat wire level that has at least a lower via portion that contacts a surface of a top electrode of a ReRAM device area ReRAM-containing stack. In other embodiments, a tall ReRAM device area bottom electrode is provided in the BEOL fat wire level and embedded in a dielectric material stack that includes a dielectric capping layer and an interlayer dielectric material layer.

Abstract: A phase change memory (PCM) cell includes an electrode, a heater electrically connected to the electrode, a PCM material electrically connected to the heater, a second electrode electrically connected to the PCM material, an electrical insulator surrounding the PCM material, and a shield positioned between the PCM material and the electrical insulator, the shield comprising a reactive-ion-etching-resistant material.

Abstract: A semiconductor structure may include a heater surrounded by a second dielectric layer, a projection liner on top of the second dielectric layer, and a phase change material layer above the projection liner. A top surface of the projection liner may be substantially flush with a top surface of the heater. The projection liner may separate the phase change material layer from the second dielectric layer. The projection liner may provide a parallel conduction path in the crystalline phase and the amorphous phase of the phase change material layer. The semiconductor structure may include a bottom electrode below and in electrical contact with the heater and a top electrode above and in electrical contact with the phase change material layer.

Abstract: The subject disclosure relates to 3D microelectronic chip packages with embedded coolant channels. The disclosed 3D microelectronic chip packages provide a complete and practical mechanism for introducing cooling channels within the 3D chip stack while maintaining the electrical connection through the chip stack. According to an embodiment, a microelectronic package is provided that comprises a first silicon chip comprising first coolant channels interspersed between first thru-silicon-vias (TSVs). The microelectronic chip package further comprises a silicon cap attached to a first surface of the first silicon chip, the silicon cap comprising second TSVs that connect to the first TSVs. A second silicon chip comprising second coolant channels can further be attached to the silicon cap via interconnects formed between a first surface of the second silicon chip and the silicon cap, wherein the interconnects connect to the second TSVs.

Abstract: A mushroom type phase change memory (PCM) cell includes a projection liner located between a PCM volume and a bottom electrode. The projection liner has been retained from a layer previously utilized as an etch stop layer during the fabrication of PCM cell and/or the fabrication of the higher level IC device. The projection liner may extend beyond the PCM sidewall(s) or side boundary. This section of the projection liner may be located or buried under a dielectric or an encapsulation spacer and may increase thickness uniformity of the projection liner below the PCM volume.

Abstract: A semiconductor structure may include a heater surrounded by a dielectric layer, a projection liner on top of the heater, a phase change material layer above the projection liner, and a top electrode contact surrounding a top portion of the phase change material layer, The projection liner may cover a top surface of the heater. The projection liner may separate the phase change material layer from the second dielectric layer and the heater. The projection liner may provide a parallel conduction path in the crystalline phase and the amorphous phase of the phase change material layer. The top electrode contact may be separated from the phase change material layer by a metal liner. The semiconductor structure may include a bottom electrode below and in electrical contact with the heater and a top electrode above and in electrical contact with the phase change material layer.

Abstract: A semiconductor structure may include a heater surrounded by a dielectric layer, a projection liner on top of the heater, a phase change material layer above the projection liner, and a top electrode contact surrounding a top portion of the phase change material layer, The projection liner may cover a top surface of the heater. The projection liner may separate the phase change material layer from the second dielectric layer and the heater. The projection liner may provide a parallel conduction path in the crystalline phase and the amorphous phase of the phase change material layer. The top electrode contact may be separated from the phase change material layer by a metal liner. The semiconductor structure may include a bottom electrode below and in electrical contact with the heater and a top electrode above and in electrical contact with the phase change material layer.

Abstract: A semiconductor structure may include a heater surrounded by a second dielectric layer. a projection liner on top of the second dielectric layer, and a phase change material layer above the projection liner. A top surface of the projection liner may be substantially flush with a top surface of the heater. The projection liner may separate the phase change material layer from the second dielectric layer. The projection liner may provide a parallel conduction path in the crystalline phase and the amorphous phase of the phase change material layer. The semiconductor structure may include a bottom electrode below and in electrical contact with the heater and a top electrode above and in electrical contact with the phase change material layer.

Abstract: A mushroom type phase change memory (PCM) cell includes a projection liner located between a PCM volume and a bottom electrode. The projection liner has been retained from a layer previously utilized as an etch stop layer during the fabrication of PCM cell and/or the fabrication of the higher level IC device. The projection liner may extend beyond the PCM sidewall(s) or side boundary. This section of the projection liner may be located or buried under a dielectric or an encapsulation spacer and may increase thickness uniformity of the projection liner below the PCM volume.

Abstract: Embodiments of the present invention are directed to forming a Resistive Random Access Memory (RRAM) device with a spacer for electrode isolation. In a non-limiting embodiment of the invention, a memory stack including a top electrode, a bottom electrode, and a dielectric layer between the top electrode and the bottom electrode is formed. A portion of the memory stack is removed to expose a sidewall of the top electrode and a spacer is formed on the sidewall of the top electrode. The spacer is positioned to encapsulate the top electrode, physically preventing a short between the top electrode and the bottom electrode.

Abstract: A method for manufacturing a semiconductor device includes forming a memory element in a dielectric layer. A first conductive layer is deposited on the dielectric layer and the memory element by atomic layer deposition, and a second conductive layer is deposited on the first conductive layer by physical vapor deposition. In the method, the first and second conductive layers are patterned into an electrode on the memory element.

Abstract: Embodiments of the present invention are directed to microchannels having varied critical dimensions for efficient cooling of semiconductor integrated circuit chip packages. In a non-limiting embodiment of the invention, a patterning stack is formed over a substrate. The patterning stack includes a hard mask, an etch transfer layer on the hard mask, and a photoresist on the etch transfer layer. A manifold trench is formed in a first region of the substrate and is recessed below a surface of the etch transfer layer. A microchannel trench is formed in a second region of the substrate to expose the surface of the etch transfer layer. The manifold trench and the microchannel trench are recessed such that the manifold trench extends into the hard mask and the microchannel trench extends into the etch transfer layer. A manifold and a microchannel are formed in the substrate by pattern transfer.

Abstract: Techniques for planarization of dielectric topography that stop in dielectric are provided. In one aspect, a method for planarization includes: depositing a first dielectric onto a wafer having a surface topography with peaks and valleys; depositing a second, different dielectric onto the first dielectric; and polishing the second dielectric down to the first dielectric to form a planar surface at an interface between the first dielectric and the second dielectric. Optionally, a follow-up CMP or etch can be performed using a ˜1:1 selective polish or etch to completely remove the second dielectric and an equivalent amount of the first dielectric to form a planar surface devoid of the peaks and valleys in the first dielectric. A device structure formed by the present techniques is also provided.

Abstract: The subject disclosure relates to 3D microelectronic chip packages with embedded coolant channels. The disclosed 3D microelectronic chip packages provide a complete and practical mechanism for introducing cooling channels within the 3D chip stack while maintaining the electrical connection through the chip stack. According to an embodiment, a microelectronic package is provided that comprises a first silicon chip comprising first coolant channels interspersed between first thru-silicon-vias (TSVs). The microelectronic chip package further comprises a silicon cap attached to a first surface of the first silicon chip, the silicon cap comprising second TSVs that connect to the first TSVs. A second silicon chip comprising second coolant channels can further be attached to the silicon cap via interconnects formed between a first surface of the second silicon chip and the silicon cap, wherein the interconnects connect to the second TSVs.

Abstract: The subject disclosure relates to 3D microelectronic chip packages with embedded coolant channels. The disclosed 3D microelectronic chip packages provide a complete and practical mechanism for introducing cooling channels within the 3D chip stack while maintaining the electrical connection through the chip stack. According to an embodiment, a microelectronic package is provided that comprises a first silicon chip comprising first coolant channels interspersed between first thru-silicon-vias (TSVs). The microelectronic chip package further comprises a silicon cap attached to a first surface of the first silicon chip, the silicon cap comprising second TSVs that connect to the first TSVs. A second silicon chip comprising second coolant channels can further be attached to the silicon cap via interconnects formed between a first surface of the second silicon chip and the silicon cap, wherein the interconnects connect to the second TSVs.

Abstract: Techniques for planarization of dielectric topography that stop in dielectric are provided. In one aspect, a method for planarization includes: depositing a first dielectric onto a wafer having a surface topography with peaks and valleys; depositing a second, different dielectric onto the first dielectric; and polishing the second dielectric down to the first dielectric to form a planar surface at an interface between the first dielectric and the second dielectric. Optionally, a follow-up CMP or etch can be performed using a ˜1:1 selective polish or etch to completely remove the second dielectric and an equivalent amount of the first dielectric to form a planar surface devoid of the peaks and valleys in the first dielectric. A device structure formed by the present techniques is also provided.