Patents by Inventor Ira G. Chayut

Ira G. Chayut has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7281232
    Abstract: A method and apparatus for checking topology layout routing is described. A method for checking topology layout routing includes accessing actual topology layout information of a circuit. Then, compliance topology information is established. Then, the method checks the actual topology layout information complies with the compliance topology information. Then, the method presents violations of the compliance topology information.
    Type: Grant
    Filed: June 23, 2004
    Date of Patent: October 9, 2007
    Assignee: Nvidia Corporation
    Inventors: Sam J. Nicolino, Jr., Ira G. Chayut
  • Patent number: 7274568
    Abstract: An apparatus and method for cooling semiconductor devices. A cooling system for semiconductor devices is disclosed and includes a semiconductor substrate, horizontal channels and a cooling medium. Specifically, the semiconductor substrate is incorporated into a die. Also, one or more horizontal channels are formed in a backside of the semiconductor substrate of the die. The horizontal channels collect thermal energy that is generated by electrical components located on a front side of the semiconductor substrate. A cooling medium circulates within the one or more horizontal channels for transferring the thermal energy away from the die.
    Type: Grant
    Filed: November 7, 2006
    Date of Patent: September 25, 2007
    Assignee: Nvidia Corporation
    Inventor: Ira G. Chayut
  • Patent number: 7180742
    Abstract: An apparatus and method for cooling semiconductor devices. A cooling system for semiconductor devices is disclosed and includes a semiconductor substrate, horizontal channels and a cooling medium. Specifically, the semiconductor substrate is incorporated into a die. Also, one or more horizontal channels are formed in a backside of the semiconductor substrate of the die. The horizontal channels collect thermal energy that is generated by electrical components located on a front side of the semiconductor substrate. A cooling medium circulates within the one or more horizontal channels for transferring the thermal energy away from the die.
    Type: Grant
    Filed: May 24, 2004
    Date of Patent: February 20, 2007
    Assignee: Nvidia Corporation
    Inventor: Ira G. Chayut
  • Patent number: 6574728
    Abstract: A computer system includes a register file and an arithmetic logic unit (ALU) for reading data from the register file. The ALU is configured to conduct data processing of the data which was and to store the results of the data processing in the register file. The computer system further includes a condition code stack configured to hold data indicative of the context results of the data processing by the ALU. The ALU is further configured to query the condition code stack for predetermined bit values to determine operations controlled by the ALU. In particular, value of a specified data item in a condition code stack is queried, and the queried value of the data item is used to implement transfer control.
    Type: Grant
    Filed: August 10, 1999
    Date of Patent: June 3, 2003
    Assignee: Cirrus Logic, Inc.
    Inventor: Ira G. Chayut