Abstract: A Monolithic Synchronous Processor (MeshSP) processes data and incorporates a mesh parallel computer architecture, primarily SIMD, thereby combining high data throughput with modest size, weight, power and cost. Each MeshSP processor node utilizes a single DSP processor element, a large internal memory of at least 128k-bytes, and separately operable computational and I/O processing sections. The processor element provides data throughput of at least 120 MFlops. The processor is programmed in ANSI C and without parallel extensions. A combination of on-chip DMA hardware and system software simplifies data I/O and interprocessor communication. The MeshSP is programmed to solve a wide variety of computationally demanding signal processing problems. A functional simulator enables MeshSP algorithms to be coded and tested on a personal computer.

Abstract: A Monolithic Synchronous Processor (MeshSP) processes data and incorporates a mesh parallel computer architecture, primarily SIMD, thereby combining high data throughput with modest size, weight, power and cost. Each MeshSP processor node utilizes a single DSP processor element, a large internal memory of at least 128k-bytes, and separately operable computational and I/O processing sections. The processor element provides data throughput of at least 120 MFlops. The processor is programmed in ANSI C and without parallel extensions. A combination of on-chip DMA hardware and system software simplifies data I/O and interprocessor communication. The MeshSP is programmed to solve a wide variety of computationally demanding signal processing problems. A functional simulator enables MeshSP algorithms to be coded and tested on a personal computer.

Abstract: A translator translates user source code into user object code such as machine code. The translator responds differently to two unique types of loops in the source code. In particular, the translator responds to a first type of loop in the source code by generating an equivalent set of object code instructions that unroll iterations of the loop. In contrast, the translator responds to a second type of loop retaining the loop in the object code. As such, the loop is not unrolled, but rather remains intact.

Abstract: In a single instruction multiple data synchronous processor, each slave processor of an array includes a computational element and an isolated slave memory. Instructions broadcast to the slave processors may be processed simultaneously with data transfers between slave memories through communications registers and between the slave memories and an I/O processor through I/O registers. A multiplexer in each slave processor selects as an input to the communications register a signal from an adjacent slave or a nonadjacent slave to bypass a column in the array. Broadcast instructions may be overridden by individual slave processors by conditional instructions which set the otherwise unused program counter of the computational element. An array master, communication master and input/out processor may process respective sets of instructions in parallel, each addressing slave memories through a common memory controller.